• Journal of Korea Foundry Society
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• v.17 no.2
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• pp.180-187
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• 1997

The influence of solidification condition on the segregation of SiC particles in the $Al-xSi/6wt%SiC_p$(x: 6, 10, 14, 18${\cdot}$wt%) composites was investigated in the study. The results are as follows: 1) During the counter-gravity unidirectional solidification of $Al-Si/SiC_p$ composites melt, most of the SiC particles are pushed to the top of the casting. 2) The SiC particles pushing in the $Al-Si/SiC_p$ composite melts are not observed, when the interface velocity of melts increases more than 1.41 ${\mu}m/sec$. 3) The SiC particles are entrapped in the interdendrite regions, when the sizes of SiC particles in the $Al-Si/SiC_p$ composites are large than ${\varphi}22{\mu}m$.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.340-340
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• 2012

최근 MOS 소자들이 게이트 산화막을 Mono-layer가 아닌 Multi-Layer을 사용하는 추세이다. Bulk와 High-k물질간의 Dangling Bond를 줄이기 위해 Passivation 층을 만드는 것을 예로 들 수 있다. 이러한 Double Layer의 쓰임이 많아지면서 계면에서의 Interface State Density의 영향도 커지게 되면서 이를 측정하는 방법에 대한 연구가 활발히 진행되고 있다. 본 연구에서는 $SiO_2$ Double Layer의 Interface State Density를 Conductance Method를 사용하여 구하는 연구를 진행하였다. Wet Oxidation과 Chemical Vapor Deposition (CVD) 공정을 이용하여 $SiO_2$ Double-layer로 증착한 후 Aluminium을 전극으로 하는 MOS-Cap 구조를 만들었다. 마지막 공정은 $450^{\circ}C$에서 30분 동안 Forming-Gas Annealing (FGA) 공정을 진행하였다. LCR meter를 이용하여 high frequency C-V를 측정한 후 North Carolina State University California Virtual Campus (NCSU CVC) 프로그램을 이용하여 Flatband Voltage를 구한 후에 Conductance Method를 측정하여 Dit를 측정하였다. 본 연구 결과 Double layer (Wet/CVD $SiO_2$)에 대해서 Conductance Method를 방법을 이용하여 Dit를 측정하는 것이 유효하다는 것을 확인 할 수 있었다. 본 실험은 앞으로 많이 쓰이고 측정될 Double layer (Wet/CVD $SiO_2$)에 대한 Interface State Density의 측정과 분석에 대한 방향을 제시하는데 도움이 될 것이라 판단된다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.12
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• pp.59-64
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• 1996

InSb MIS devices prepared by remote PECVD SiO$_{2}$ were fabricated. The SiO$_{2}$ films on InSb were deposited at atemperature range of 67~190$^{\circ}$C. The effects of deposition temperature on the structural characteristics of the SiO$_{2}$ films evaluated Auger electron spectroscopy showed that atomic raito of silicon to oxygen was 0.5 and composition toms were distributed uniformaly throuout the oxide film. The transition region is about 100$\AA$ for SiO$_{2}$/InSb interface. The leakage current density at 1MV/cm and the breakdownelectric field of the MiS device using SiO$_{2}$ film deposited at 105$^{\circ}$C were about 22 nA/cm$^{2}$ and 3.5MV/cm, respectively. The interface-state density at mid-bandgap extracted from 1 MHz high frequency C-V measurement was about 2X10$^{11}$ cm$^{-2}$eV$^{-1}$.

• Composites Research
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• v.13 no.6
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• pp.23-29
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• 2000

The internal residual stresses within the multilayered structure with sharp interface induced by the difference in thermal expansion coefficient between the materials of adjacent layers often provide the source of failure such as delamination of interfaces etc. Recent development of the multilayered structure with functionally graded interface would be the solution to prevent this kind of failure. However a systematic thermo-mechanical analysis is needed for the customized structural design of multilayered structure. In this study, theoretical model for the thermo-mechanical analysis is developed for multilayered structures of the $Al-SiC_p$ functionally graded composite for electronic packaging. The evolution of curvature and internal stresses in response to temperature variations is presented for the different combinations of geometry. The resultant analytical solutions are used for the optimal design of the multilayered structures with functionally graded interface as well as with sharp interface.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.10
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• pp.859-863
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• 2007

Aluminum oxide films were deposited on n-type 6H-SiC(0001) substrates by RF magnetron sputtering technique for MIS devices applications. Well-behaved C-V characteristics were obtained measured in MIS capacitors structures. The calculated interface trap density measured at $300^{\circ}C$ was about $4.6{\times}10^{10}/cm^2\;eV$ in the upper half of the bandgap. The gate leakage current densities of the MIS structures were about $10^{-8}A/cm^2$ and about $10^{-6}A/cm^2$ measured at room temperature and at $300^{\circ}C$ for a ${\pm}1\;MV/cm$, respectively These results indicate that the interface property of this structure is enough quality to MIS devices applications.

• Korean Journal of Materials Research
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• v.11 no.2
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• pp.71-75
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• 2001

The reaction stability of nickel with side-wall materials of SiO$_2$ and Si$_3$N$_4$ on p-type 4"(100) Si substrate were investigated. Ni on 1300 $\AA$ thick SiO$_2$ and 500 $\AA$ - thick Si$_3$N$_4$ were deposited. Then the samples were annealed at 400, 500, 750 and 100$0^{\circ}C$ for 30min, and the residual Ni layer was removed by a wet process. The interface reaction stability was probed by AES depth Profiling. No reaction was observed at the Ni/SiO$_2$ and Ni/Si$_3$N$_4$, interfaces at 400 and 50$0^{\circ}C$. At 75$0^{\circ}C$, no reaction occurred at Ni/SiO$_2$ interface, while $NiO_x$ and Si$_3$N$_4$ interdiffused at Ni/Si$_3$N$_4$ interface. At 100$0^{\circ}C$, Ni layers on SiO$_2$ and Si$_3$N$_4$ oxidized into $NiO_x$ and then $NiO_x$ interacted with side-wall materials. Once $NiO_x$ was formed, it was not removed in wet etching process and easily diffused into sidewall materials, which could lead to bridge effect of gate-source/drain.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.346-349
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• 1988

Conductance technique is the moat accurate method and gives more detailed information about interface of the MIS structure than other methods. With the measurement of the equivalent parallel conductance and capacitance, the characterization of Si-SiN interface is developed. The interface state density of Si-SiN is obtained by $8{\times}10^{11}$ - $6{\times}10^{12}(eV^{-1}cm^{-2}$). After the positive B-T stress is performed on the sample, the interface state density gets increased. The interface state density is not effected by the D.C. stress.

• ETRI Journal
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• v.19 no.1
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• pp.26-35
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• 1997

The substrate effects on solid-phase crystallization of amorphous silicon (a-Si) films deposited by low-pressure chemical vapor deposition (LPCVD) using $Si_2H_6$ gas have been extensively investigated. The a-Si films were prepared on various substrates, such as thermally oxidized Si wafer ($SiO_2$/Si), quartz and LPCVD-oxide, and annealed at 600$^{\circ}C$ in an $N_2$ ambient for crystallization. The crystallization behavior was found to be strongly dependent on the substrate even though all the silicon films were deposited in amorphous phase. It was first observed that crystallization in a-Si films deposited on the $SiO_2$/Si starts from the interface between the a-Si and the substrate, so called interface-interface-induced crystallization, while random nucleation process dominates on the other substrates. The different kinetics and mechanism of solid-phase crystallization is attributed to the structural disorderness of a-Si films, which is strongly affected by the surface roughness of the substrates.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.3
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• pp.468-473
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• 2003

In this paper, for enhancement of property on a-Si:H TFTs We measure interface characteristics of ferroelectrics thin film and a-Si:H thin film. First, SrTiO$_3$ thin film is deposited bye-beam evaporation. Deposited films are annealed for 1 hour in N2 ambient at $150^{\circ}C∼600^{\circ}C$. Dielectric characteristics of deposited SrTiO$_3$ films are very good because dielectric constant shows 50∼100 and breakdown electric field are 1 ∼ 1.5 MV/cm. a-SiN:H,a-Si:H(n-type a-Si:H) are deposited onto SrTiO$_3$ film to make MFNS(Meta1/ferroelectric/a-SiN:H/a-Si:H) by PECVD. After the C-V measurement for interface characteristics, MFNS structure shows no difference with MNS(Metal/a-SiN:H/a-Si:H) structure in C-V characteristics but the insulator capacitance value of MFNS structure is much higher than the MNS because of high dielectric constant of ferroelectric.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.10
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• pp.438-442
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• 2005

Si nanocrystal (Si NC) memory device has several advantages such as better retention, lower operating voltage, reduced punch-through and consequently a smaller cell area, suppressed leakage current. However, the physical and electrical reasons for this behavior are not completely understood but could be related to interface states of Si NCs. In order to find out this effect, we characterized electrical properties of Si NCs embedded in a SiO$_{2}$ layer by scanning probe microscopy (SPM). The Si NCs were generated by the laser ablation method with compressed Si powder and followed by a sharpening oxidation. In this step Si NCs are capped with a thin oxide layer with the thickness of 1$\~$2 nm for isolation and the size control. The size of 51 NCs is in the range of 10$\~$50 m and the density around 10$^{11}$/cm$^{2}$ It also affects the interface states of Si NCs, resulting in the change of electrical properties. Using a conducting tip, the charge was injected directly into each Si NC, and the image contrast change and dC/dV curve shift due to the trapped charges were monitored. The results were compared with C-V characteristics of the conventional MOS capacitor structure.