• Journal of the Microelectronics and Packaging Society
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• 제16권4호
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• pp.9-15
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• 2009

Compared to the flip-chip process using solder bumps, Cu pillar bump technology can accomplish much finer pitch without compromising stand-off height. Flip-chip process with Cu pillar bumps can also be utilized in radio-frequency packages where large gap between a chip and a substrate as well as fine pitch interconnection is required. In this study, Cu pillars with and without Sn caps were electrodeposited and flip-chip-bonded together to form the Cu-Sn-Cu sandwiched joints. Contact resistances and die shear forces of the Cu-Sn-Cu sandwiched joints were evaluated with variation of the height of the Sn cap electrodeposited on the Cu pillar bump. The Cu-Sn-Cu sandwiched joints, formed with Cu pillar bumps of $25-{\mu}m$ diameter and $20-{\mu}m$ height, exhibited the gap distance of $44{\mu}m$ between the chip and the substrate and the average contact resistance of $14\;m{\Omega}$/bump without depending on the Sn cap height between 10 to $25\;{\mu}m$.

• Journal of the Microelectronics and Packaging Society
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• 제14권1호
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• pp.33-38
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• 2007

We studied a bonding at low temperature using polymer bump and Non-Conductive Adhesive (NCA), and studied the reliability of the polymer bump/Al pad joints. The polymer bumps were formed on oxidized Si substrates by photolithography process, and the thin film metals were formed on the polymer bumps using DC magnetron sputtering. The substrate used was AL metallized glass. The polymer bump and Al metallized glass substrates were joined together at $80^{\circ}C$ under various pressure. Two NCAs were applied during joining. Thermal cycling test ($0^{\circ}C-55^{\circ}C$, cycle/30 min) was carried out up to 2000 cycles to evaluate the reliability of the joints. The bondability was evaluated by measuring the contact resistance of the joints through the four point probe method, and the joints were observed by Scanning Electron Microscope (SEM). The contact resistance of the joints was $70-90m{\Omega}$ before the reliability test. The joints of the polymer bump/Al pad were damaged by NCA filler particles under pressure above 200 MPa. After reliability test, some joints were electrically failed since thinner metal layers deposited at the edge of bumps were disconnected.

• Journal of the Microelectronics and Packaging Society
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• 제26권2호
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• pp.31-43
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• 2019

In this study, polymer elastic bumps were fabricated for the flexible electronic package flip chip bonding and the viscoelastic and viscoplastic behavior of the polymer elastic bumps according to the temperature and load were analyzed using FEM and experiments. The polymer elastic bump is easy to deform by the bonding load, and it is confirmed that the bump height flatness problem is easily compensated and the stress concentration on thin chip is reduced remarkably. We also develop a spiral cap type and spoke cap type polymer elastic bump of $200{\mu}m$ diameter to complement Au metal cap crack phenomenon caused by excessive deformation of polymer elastic bump. The proposed polymer elastic bumps could reduce stress of metal wiring during bump deformation compared to metal cap bump, which is completely covered with metal wiring because the metal wiring on these bumps is partially patterned and easily deformable pattern. The spoke cap bump shows the lowest stress concentration in the metal wiring while maintaining the low contact resistance because the contact area between bump and pad was wider than that of the spiral cap bump.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 한국마이크로전자및패키징학회 2004년도 추계 기술심포지움 초록집
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• pp.61-61
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• 2004

• Proceedings of the KWS Conference
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• 대한용접접합학회 2006년도 춘계 학술대회 개요집
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• pp.215-217
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• 2006

• Proceedings of the KWS Conference
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• 대한용접접합학회 2006년도 춘계 학술대회 개요집
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• pp.203-205
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• 2006

• Proceedings of the KWS Conference
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• 대한용접접합학회 2005년도 춘계학술발표대회 개요집
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• pp.40-42
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• 2005

• Journal of Institute of Control, Robotics and Systems
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• 제21권12호
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• pp.1115-1121
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• 2015

Fast inspection of solder ball bumps in ball grid array (BGA) is an important issue in the flip chip bonding technology. Particularly, semiconductor industry has required faster and more accurate inspection of micron-size solder bumps in flip chip bonding, as the density of balls increase dramatically. In this paper, we describe an inspection approach of BGA balls by using 5-step ring illumination device and normalized cross-correlation (NCC) method. The images of BGA ball by the illumination device show unique and distinguishable characteristic contours by their 3-D shapes, which are called as "iso-slope contours". Template images of reference ball samples can be produced artificially by the hybrid reflectance model and 3D data of balls. NCC values between test and template samples are very robust and reliable under well-structured condition. The 200 samples on real wafer are tested and show good practical feasibility of the proposed method.

• Journal of the Microelectronics and Packaging Society
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• 제19권3호
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• pp.15-20
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• 2012

In electronics industry, the coming electronic devices will be expected to be high integration and convergence electronics. And also, it will be expected that the coming electronics will be flexible, bendable and wearable electronics. Therefore, the demands and interests of bonding technology between flexible substrate and chip for mobile electronics, e-paper etc. have been increased because of weight and flexibility of flexible substrate. Considering fine pitch for high density and thermal damage of flexible substrate during bonding process, the micro solder bump technology for high density and low temperature bonding process for reducing thermal damage will be required. In this study, we researched on bonding technology of chip and flexible substrate by using 25um Cu pillar bumps and Sn-Bi solder bumps were formed by electroplating. From the our study, we suggest technology on Cu pillar bump formation, Sn-Bi solder bump formation, and bonding process of chip and flexible substrate for the coming electronics.

• Journal of the Korean Society for Precision Engineering
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• 제20권5호
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• pp.218-224
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• 2003

This paper describes a novel MEMS integration technique on a CMOS chip. MEMS integration on CMOS circuit has many advantages in view of manufacturing cost and reliability. The surface topography of a CMOS chip from a commercial foundry has 0.9 ${\mu}{\textrm}{m}$ bumps due to the conformal coating on aluminum interconnect patterns, which are used for addressing each MEMS element individually. Therefore, it is necessary to achieve a flat mirror-like CMOS chip fer the microelectromechanical system (MEMS) such as micro mirror array. Such CMOS chip needs an additional thickness of the dielectric passivation layer to ease the subsequent planarization process. To overcome a temperature limit from the aluminum thermal degradation, this study uses RF sputtering of silicon nitride at low temperature and then polishes the CMOS chip together with the surrounding dummy pieces to define a polishing plane. Planarization reduces 0.9 ${\mu}{\textrm}{m}$ of the bumps to less than 25 nm.