• Title/Summary/Keyword: breakdown structure

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Asymmetric Rolling as Means of Texture and Ridging Control and Grain Refinement (집합조직과 이랑형표면결함의 제어 및 결정립 미세화 수단으로서의 비대칭압연)

  • Lee D.N.
    • Proceedings of the Korean Society for Technology of Plasticity Conference
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    • 2004.08a
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    • pp.11-18
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    • 2004
  • Asymmetric rolling, in which the circumferential velocities of the upper and lower rolls are different, can give rise to intense plastic shear strains and in turn shear deformation textures through the sheet thickness. The ideal shear deformation texture of fcc metals can be approximated by the <111> // ND and $\{001\}<110>$ orientations, among which the former improves the deep drawability. The ideal shear deformation texture for bcc metals can be approximated by the Goss $\{110\}<001>\;and\;\{112\}<111>$ orientations, among which the former improves the magnetic permeability along the <100> directions and is the prime orientation in grain oriented silicon steels. The intense shear strains can result in the grain refinement and hence improve mechanical properties. Steel sheets, especially ferritic stainless steel sheets, and aluminum alloy sheets may exhibit an undesirable surface roughening known as ridging or roping, when elongated along RD and TD, respectively. The ridging or roping is caused by differently oriented colonies, which are resulted from the <100> oriented columnar structure in ingots or billets, especially for ferritic stainless steels, that is not easily destroyed by the conventional rolling. The breakdown of columnar structure and the grain refinement can be achieved by asymmetric rolling, resulting in a decrease in the ridging problem.

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Development of 900 V Class MOSFET for Industrial Power Modules (산업 파워 모듈용 900 V MOSFET 개발)

  • Chung, Hunsuk
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.33 no.2
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    • pp.109-113
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    • 2020
  • A power device is a component used as a switch or rectifier in power electronics to control high voltages. Consequently, power devices are used to improve the efficiency of electric-vehicle (EV) chargers, new energy generators, welders, and switched-mode power supplies (SMPS). Power device designs, which require high voltage, high efficiency, and high reliability, are typically based on MOSFET (metal-oxide-semiconductor field-effect transistor) and IGBT (insulated-gate bipolar transistor) structures. As a unipolar device, a MOSFET has the advantage of relatively fast switching and low tail current at turn-off compared to IGBT-based devices, which are built on bipolar structures. A superjunction structure adds a p-base region to allow a higher yield voltage due to lower RDS (on) and field dispersion than previous p-base components, significantly reducing the total gate charge. To verify the basic characteristics of the superjunction, we worked with a planar type MOSFET and Synopsys' process simulation T-CAD tool. A basic structure of the superjunction MOSFET was produced and its changing electrical characteristics, tested under a number of environmental variables, were analyzed.

Electrical Characteristics of Enhancement-Mode n-Channel Vertical GaN MOSFETs and the Effects of Sidewall Slope

  • Kim, Sung Yoon;Seo, Jae Hwa;Yoon, Young Jun;Kim, Jin Su;Cho, Seongjae;Lee, Jung-Hee;Kang, In Man
    • Journal of Electrical Engineering and Technology
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    • v.10 no.3
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    • pp.1131-1137
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    • 2015
  • Gallium nitride (GaN) is a promising material for next-generation high-power applications due to its wide bandgap, high breakdown field, high electron mobility, and good thermal conductivity. From a structure point of view, the vertical device is more suitable to high-power applications than planar devices because of its area effectiveness. However, it is challenging to obtain a completely upright vertical structure due to inevitable sidewall slope in anisotropic etching of GaN. In this letter, we design and analyze the enhancement-mode n-channel vertical GaN MOSFET with variation of sidewall gate angle by two-dimensional (2D) technology computer-aided design (TCAD) simulations. As the sidewall slope gets closer to right angle, the device performances are improved since a gradual slope provides a leakage current path through the bulk region.

Electrical characteristics of polycrystalline 3C-SiC thin film diodes (다결정 3C-SiC 박막 다이오드의 전기적 특성)

  • Chung, Gwiy-Sang;Ahn, Jeong-Hak
    • Journal of Sensor Science and Technology
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    • v.16 no.4
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    • pp.259-262
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    • 2007
  • This paper describes the electrical characteristics of polycrystalline (poly) 3C-SiC thin film diodes, in which poly 3C-SiC thin films on n-type and p-type Si wafers, respectively, were deposited by APCVD using HMDS, $H_{2}$, and Ar gas at $1150^{\circ}C$ for 3 hr. The schottky diode with Au/poly 3C-SiC/Si (n-type) structure was fabricated. Its threshold voltage ($V_{bi}$), breakdown voltage, thickness of depletion layer, and doping concentration ($N_{D}$) value were measured as 0.84 V, over 140 V, 61 nm, and $2.7{\times}10^{19}cm^{-3}$, respectively. Moreover, for the good ohmic contact, Al/poly 3C-SiC/Si (n-type) structure was annealed at 300, 400, and $500^{\circ}C$, respectively for 30 min under the vacuum condition of $5.0{\times}10^{-6}$ Torr. Finally, the p-n junction diodes fabricated on the poly 3C-Si/Si (p-type) were obtained like characteristics of single 3CSiC p-n junction diode. Therefore, poly 3C-SiC thin film diodes will be suitable for microsensors in conjunction with Si fabrication technology.

Capacitance Properties of Nano-Structure Controlled Alumina on Polymer Substrate (폴리머 기판위에 형성된 나노구조제어 알루미나의 캐패시터 특성)

  • Jung, Seung-Won;Min, Hyung-Sub;Han, Jeong-Whan;Lee, Jeon-Kook
    • Korean Journal of Materials Research
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    • v.17 no.2
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    • pp.81-85
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    • 2007
  • Embedded capacitor technology can improve electrical perfomance and reduce assembly cost compared with traditional discrete capacitor technology. To improve the capacitance density of the $Al_2O_3$ based embedded capacitor on Cu cladded fiber reinforced plastics (FR-4), the specific surface area of the $Al_2O_3$ thin films was enlarged and their surface morphologies were controlled by anodization process parameters. From I-V characteristics, it was found that breakdown voltage and leakage current were 23 V and $1{\times}10^{-6}A/cm^2$ at 3.3 V, respectively. We have also measured C-V characteristics of $Pt/Al_2O_3/Al/Ti$ structure on CU/FR4. The capacitance density was $300nF/cm^2$ and the dielectric loss was 0.04. This nano-porous $Al_2O_3$ is a good material candidate for the embedded capacitor application for electronic products.

The interfacial properties of th eanneled SiO$_{2}$/TiW structure (열처리된 SiO$_{2}$/TiW 구조의 계면 특성)

  • 이재성;박형호;이정희;이용현
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.3
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    • pp.117-125
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    • 1996
  • The variation of the interfacial and the electrical properties of SiO$_{2}$TiW layers as a function of anneal temperature was extensively investigated. During the deposition of SiO$_{2}$ on TiW chemical bonds such as SiO$_{2}$, TiW, WO$_{3}$, WO$_{2}$ TiO$_{2}$ Ti$_{2}$O$_{5}$ has been created at the SiO$_{2}$/TiW interface. At the anneal temperature of 300$^{\circ}C$, WO$_{3}$ and TiO$_{2}$ bonds started to break due to the reduction phenomena of W and Ti and simultaneously the metallic W and Ti bonds started to create. Above 500$^{\circ}C$, a part of Si-O bonds was broken and consequently Ti/W silicide was formed. Form the current-voltage characteristics of Al/Sico$_{2}$(220$\AA$)/TiW antifuse structure, it was found that the breakdown voltage of antifuse device wzas decreased with increasing annealing temperature for SiO$_{2}$(220$\AA$)/TiW layer. When r, the insulating property of antifuse device of the deterioration of intermetallic SiO$_{2}$ film, caused by the influw of Ti and W.W.

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A Plan of Project Information Management through Analysis of Drafting Process for Transportation Planning (양중계획입안 프로세스의 구조화를 통한 프로젝트 정보관리 방안)

  • Kim, Jin-Ho
    • Journal of the Korea Institute of Building Construction
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    • v.8 no.3
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    • pp.101-109
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    • 2008
  • As the number of high-rise building construction projects grows up, the subject of the transportation planning has become one of the grave issue. however important decision making are made by the experience of the a planner without the rational plans for information sharing. therefore, the purpose of this study is to suggest a plan of prefect information management not only for describing drafting process for transportation planning but also for systematizing information used in the procurement, transportation and construction phase to achieve these objectives, this study 1)analyzes the prior theory about transportation planning, 2)performs a case study of actual project to embody the problems of site management by analyzing the results of interviewing experts. In conclusion, the following factors are systematized : 1)the structure of drafting process for transportation planning, 2)the contents of information used in the procurement, transportation and construction phase, 3)the actual condition of code breakdown structure in transportation Planning phase. It is anticipated that the proposed methodology would be able to improve information management among the related engineers and accumulated data that might be used in similar construction projects in Korea.

Analysis of Electrical Characteristics According to the Pillar Spacing of 4.5 kV Super Junction IGBT (4.5 kV급 Super Junction IGBT의 Pillar 간격에 따른 전기적 특성 분석)

  • Lee, Geon Hee;Ahn, Byoung Sup;Kang, Ey Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.33 no.3
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    • pp.173-176
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    • 2020
  • This study focuses on a pillar in which is implanted a P-type maneuver under a P base. This structure is called a super junction structure. By inserting the pillar, the electric field concentrated on the P base is shared by the pillar, so the columns can be dispersed while maintaining a high breakdown voltage. Ten pillars were generated during the multi epitaxial process. The interval between pillars is varied to optimize the electric field to be concentrated on the pillar at a threshold voltage of 6 V, a yield voltage of 4,500 V, and an on-state voltage drop of 3.8 V. The density of the filler gradually decreased when the interval was extended by implanting a filler with the same density. The results confirmed that the size of the depletion layer between the filler and the N-epitaxy layer was reduced, and the current flowing along the N-epitaxy layer was increased. As the interval between the fillers decreased, the cost of the epitaxial process also decreased. However, it is possible to confirm the trade-off relationship that deteriorated the electrical characteristics and efficiency.

Reliability testing of InGaAs Waveguide Photodiodes for 40-Gbps Optical Receiver Applications (40-Gbps급 InGaAs 도파로형 포토다이오드의 신뢰성 실험)

  • Joo, Han-Sung;Ko, Young-Don;Yun, Il-Gu
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07a
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    • pp.13-16
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    • 2004
  • The reliability of 1.550m-wavelength InGaAs mesa waveguide photodiodes(WGPDs), which developed for 40-Gbps optical receiver applications, fabricated by metal organic chemical vapor deposition is investigated. Reliability is examined by both high-temperature storage tests and the accelerated life tests by monitoring dark current and breakdown voltage. The median device lifetime and the activation energy of the degradation mechanism are computed for WGPD test structures. From the accelerated life test results, the activation energy of the degradation mechanism and median lifetime of these devices in room temperature are extracted from the log-normal failure model by using average lifetime and the standard deviation of that lifetime in each test temperature. It is found that the WGPD structure yields devices with the median lifetime of much longer than $10^6$ h at practical use conditions. Consequently, this WGPD structure has sufficient characteristics for practical 40-Gbps optical receiver modules.

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A Deriving methodologies for OT&E items using WBS when acquiring a weapon system (무기체계 획득시 WBS를 활용한 운용시험평가 항목 도출방법 개발)

  • Jong Wan, Park;Hee Tae, Jeong
    • Journal of the Korean Society of Systems Engineering
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    • v.18 no.2
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    • pp.1-10
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    • 2022
  • In general, similar or previous projects are mainly referred to in order to derive operational test and evaluation(OT&E) items after acquiring weapon system. The idea that a more systematic method is needed is spreading because some of OT&E items derived in this process are redundant or unnecessary. Therefore, in this topic, we plan to use WBS, a tool that classifies components into a hierarchical structure and manages development easily to achieve the weapon system development goal. In addition, the WBS tool is applied to the medium-sized standard vehicle project, which is currently being research and developed, to effectively derive OT&E items. As a result of deriving OT&E items by applying WBS to the vehicle development field and electric devices of the medium-sized standard vehicle project, the operability and relationship were judged early, and then contents of the evaluation items could be written substantially while working on environmental adaptability. In the future, it is judged that the efficiency will be increased if the method discussed in this paper is applied when deriving the OT&E items from the R&D development project.