• The Journal of the Acoustical Society of Korea
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• v.19 no.8
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• pp.68-77
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• 2000

Line special frequency (LSF) parameters have been widely used in low bit-rate speech coding due to their efficiency for representing the short-time speech spectrum. In this paper, a new distance measure based on the masking properties of human ear is proposed for quantizing LSF parameters whereas most conventional quantization methods are based on the weighted Euclidean distance measure. The proposed method derives the perceptual distance measure from the definition of noise-to-mask ratio (NMR) which has high correspondence with the actual distortion received in the human ear and uses it for quantizing LSF parameters. In addition, we propose an adaptive bit allocation scheme, which allocates minimal bits to LSF parameters maintaining the perceptual transparency of given speech frame for reducing the average bit-rates. For the performance evaluation, we has shown the ratio of perceptually transparent frames and the corresponding average bit-rates for the conventional and proposed methods. By jointly combining the proposed distance measure and adaptive bit allocation scheme, the proposed system requires only 770 bps for obtaining 95.5% perceptually transparent frames, while the conventional systems produce 89.9% at even 1800 bps.

• The KIPS Transactions:PartB
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• v.18B no.6
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• pp.349-354
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• 2011

In ROI processing of JPEG2000, a region of large image indicated by the user must be processed preferentially, because it takes a considerable amount of time to display the full image. When the user indicates a region of the outlined image, then the browser masks the region and sends the mask information to the server that transmitted the outlined image. The server that receives the mask information preferentially sends the corresponding code blocks. Here, a quick generation of mask information is important. In this paper, we use 48 predefined mask patterns, which are defined according to the distribution shape of ROI and background to reduce the computing time. As a result, compared to other methods that precisely handles the ROI and background, the processing time of the method is remarkably reduced, but the quality is short of the existing methods just a little bit.

• ETRI Journal
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• v.45 no.4
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• pp.615-626
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• 2023

Under limited transmission conditions, many factors affect the efficiency of video transmission. During the flight of an unmanned aerial vehicle (UAV), frequent network switching often occurs, and the channel transmission condition changes rapidly, resulting in low-video transmission efficiency. This paper presents an efficient video coding flow for UAVs working in the 5G nonstandalone network and proposes two bit controllers, including time and spatial bit controllers, in the flow. When the environment fluctuates significantly, the time bit controller adjusts the depth of the recursive codec to reduce the error propagation caused by excessive network inference. The spatial bit controller combines the spatial bit mask with the channel quality multiplier to adjust the bit allocation in space to allocate resources better and improve the efficiency of information carrying. In the spatial bit controller, a flexible mini graph is proposed to compute the channel quality multiplier. In this study, two bit controllers with end-to-end codec were combined, thereby constructing an efficient video coding flow. Many experiments have been performed in various environments. Concerning the multi-scale structural similarity index and peak signal-to-noise ratio, the performance of the coding flow is close to that of H.265 in the low bits per pixel area. With an increase in bits per pixel, the saturation bottleneck of the coding flow is at the same level as that of H.264.

• Transactions of the Society of Information Storage Systems
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• v.7 no.1
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• pp.42-46
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• 2011

Holographic Data Storage System (HDSS), one of the next generation data storage devices, is a 2-dimensional page oriented memory system using volume hologram. HDSS has many noise sources such as crosstalk, scattering and inter pixel interference, etc. The noise source is changing intensity of the light used for carrying the data signal in HDSS. The inter pixel interference results in decrease of Signal to Noise Ratio and increase of Bit Error Rate. In order to improve these problems, this paper proposes to compensate the inter pixel interference with simple interference mask.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.5
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• pp.55-59
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• 2014

Multi-band and multi-mode transmitters are needed for SDR and CR. Recently many types of polar transmitters have been studied in order to implement a multi-band and multi-mode transmitter. Polar transmitters have many advantages, such as a simple structure, high efficiency and etc. In this paper we consider the number of D/A bit and the effects of a delay mismatch as design parameters for implementing polar transmitters. From the simulation we know that a 10 bit D/A is sufficient and a delay mismatch must be maintained small than 1/64 chip for satisfying the spectrum mask characteristics. We implement a polar transmitter based on the design parameters and the measured output signal meet the spectrum mask of 800MHz CDMA.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.399-402
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• 2004

This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.

• Journal of Korea Multimedia Society
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• v.9 no.11
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• pp.1445-1454
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• 2006

To compress a specific part of an image with high quality or to transfer it, JPEG2000 standard offers an ROI(Region-of-Interest) image coding method. What is important in ROI coding is to process relative importance between ROI and background and to process ROI mask. We propose an adaptive ROI coding method supplemented the existing Implicit ROI coding and Modified implicit ROI coding to improve image quality and reduce ROI mask information. The proposed method is an EBCOT-based ROI coding that extracts ROI from the compressed bitstream, and gets the ROI mask information by classifying the codeblocks into 6 patterns. The information includes the pattern type(3bit) and the width(5bit) expressing the boundary between two regions for each codeblock. As a result, the method shows an excellent compression performance in ROI region as well as in the whole region of an image.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.821-827
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• 2001

A new low power charge-recycling ROM architecture is proposed. The charge-recycling ROM uses charge-recycling method in bit lines of ROM to save the power consumption. About 90% of the total power used in the ROM is consumed in bit lines. With the proposed method, power consumption in ROM bit lines can be reduced asymptotically to zero if the number of bit lines is infinite and the sense amplifiers detect infinitely small voltage difference. However, the real sense amplifiers cannot sense very small voltage difference. Therefore, reduction of power consumption is limited. The simulation results show that the charge-recycling ROM only consumes 13% ~ 78% of the conventional low power contact programming mask ROM.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.3 s.234
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• pp.418-424
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• 2005

We present the design, fabrication and experimental results of 4-bit digital microinjectors, whose ejected droplet volumes are adjusted by the digital operation of a 4-bit microheater array. We design the reference microinjectors as well as its comparative test structures. In the fabrication process, we use a five-mask micromachining process and the total chip size of the fabricated microinjector is $7,640{\mu}m{\times}5,260{\mu}m.$ We measure the ejected droplet volumes and velocities, which are adjusted from $12.1{\pm}1.0~55.6{\pm}14.7pl\;and\;2.3{\pm}0.1~15.7{\pm}0.8m/s.$ respectively, depending on the 15 possible combinations of 4-bit microheater array. We also experimentally characterize the effect of geometric variation including the microheater size, inter-microheater gap, microchannel width and sequential operation of microheater array on the ejected droplet volume and velocity. Among these parameters, we find that the microheater size is the most dominant parameter affected to the ejected droplet volumes and velocities. Thus, the present microinjector has a potential for application to the high-resolution inkjet printers with multiple gray levels or high-precision fluid injectors with variable volume control.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.788-791
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• 2010

We design 64-bit ROM IP for RFID tag chips using printed CMOS non-volatile memory IP design technology for a printed CMOS process. The proposed 64-bit ROM circuit is using ETRI's $0.8{\mu}m$ CMOS porocess, and is expected to reduce process complexity and cost of RFID tag chips compared to that using a conventional silicon fabrication based on a complex lithography process because the poly layer in a gate terminal is using printing technology of imprint process. And a BL precharge circuit and a BL sense amplifier is not required for the designed cell circuit since it is composed of a transmission gate instead of an NMOS transistor of the conventional ROM circuit. Therefore an output datum is only driven by a DOUT buffer circuit. The Operation current and layout area of the designed ROM of 64 bits with an array of 8 rows and 8 columns using $0.8{\mu}m$ ROM process is $9.86{\mu}A$ and $379.6{\times}418.7{\mu}m^2$.