• Title/Summary/Keyword: bit line

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An Error Control Line Code Based on an Extended Hamming Code (확대 Hamming 부호를 이용한 오류제어선로부호)

  • 김정구;정창기;이수인;주언경
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.5
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    • pp.912-919
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    • 1994
  • A new error control line code based on an extended Hamming code is proposed and its performance is analyzed in this paper. The proposed code is capable of single error correction and double error detection since its minimum Hamming distance is 4. In addition, the error detection capability can be oncreased due to the redundancy bit used for line coding. As a result, the proposed code shows lower code rate, but better spectral characteristics in low frequency region and lower residual bit error rate than the conventional error correction line code using Hamming (7, 4) code.

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Design of a 32-Bit eFuse OTP Memory for PMICs (PMIC용 32bit eFuse OTP 설계)

  • Kim, Min-Sung;Yoon, Keon-Soo;Jang, Ji-Hye;Jin, Liyan;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.10
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    • pp.2209-2216
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    • 2011
  • In this paper, we design a 32-bit eFuse OTP memory for PMICs using MagnaChip's $0.18{\mu}m$ process. We solve a problem of an electrical shortage between an eFuse link and the VSS of a p-substrate in programming by placing an n-well under the eFuse link. Also, we propose a WL driver circuit which activates the RWL (read word-line) or WWL (write word-line) of a dual-port eFuse OTP memory cell selectively when a decoded WERP (WL enable for read or program) signal is inputted to the eFuse OTP memory directly. Furthermore, we reduce the layout area of the control circuit by removing a delay chain in the BL precharging circuit. We'can obtain an yield of 100% at a program voltage of 5.5V on 94 manufactured sample dies when measured with memory tester equipment.

Perceptual and Adaptive Quantization of Line Spectral Frequency Parameters (선 스펙트럼 주파수의 청각 적응 부호화)

  • 한우진;김은경;오영환
    • The Journal of the Acoustical Society of Korea
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    • v.19 no.8
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    • pp.68-77
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    • 2000
  • Line special frequency (LSF) parameters have been widely used in low bit-rate speech coding due to their efficiency for representing the short-time speech spectrum. In this paper, a new distance measure based on the masking properties of human ear is proposed for quantizing LSF parameters whereas most conventional quantization methods are based on the weighted Euclidean distance measure. The proposed method derives the perceptual distance measure from the definition of noise-to-mask ratio (NMR) which has high correspondence with the actual distortion received in the human ear and uses it for quantizing LSF parameters. In addition, we propose an adaptive bit allocation scheme, which allocates minimal bits to LSF parameters maintaining the perceptual transparency of given speech frame for reducing the average bit-rates. For the performance evaluation, we has shown the ratio of perceptually transparent frames and the corresponding average bit-rates for the conventional and proposed methods. By jointly combining the proposed distance measure and adaptive bit allocation scheme, the proposed system requires only 770 bps for obtaining 95.5% perceptually transparent frames, while the conventional systems produce 89.9% at even 1800 bps.

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A Low-Power ECC Check Bit Generator Implementation in DRAMs

  • Cha, Sang-Uhn;Lee, Yun-Sang;Yoon, Hong-Il
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.6 no.4
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    • pp.252-256
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    • 2006
  • A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80nm 1Gb DRAM implementation.

Composition Rule of Character Codes to efficiently transmit the Character Code in HDLC(High-level Data Link Control) Protocol (HDLC(High-level Data Link Control) 프로토콜에서 효율적 문자부호 전송을 위한 문자부호화 규칙)

  • Hong, Wan-Pyo
    • The Journal of the Korea institute of electronic communication sciences
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    • v.7 no.4
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    • pp.753-760
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    • 2012
  • This paper is to show the character coding rule in computer and information equipment etc to improve the transmission efficiency in telecommunications. In the transmission system, the transmission efficiency can be increased by applying the proper character coding method. In datalink layer, HDSL ptotocol use FLAG byte to identify the frame to frame which consists of data bit stream and other control bytes. FLAG byte constits of "01111110". When data bit stream consist of the consecutive 5-bit "1" after "0", the decoder can not distinguish whether the data bit sequence is flag bit stream or data bit stream. To solve the problem, when the line coder in transmitter detects the consecutive 5-bits "1" after "0" in the input data stream, inserts violently the "0" after 5th "1" of the consecutive 5-bit "1" after "0". As a result, when the characters are decoded with the above procedure, the efficiency of system should be decreased. This paper shows the character code rule to minimize the consecutive 5-bits "1" after "0" when the code is given to each characters.

A Study on the Implementation of DS/SS Power Line Communication System for Burst-Format Data Transmission (버스트형 데이터 전송을 위한 DS/SS 전력선 통신시스템의 실현에 관한 연구)

  • 강병권;이재경;신광영;황금찬
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.16 no.11
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    • pp.1054-1062
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    • 1991
  • In this paper a communication system using direct sequence spread spectrum (DS/SS) technique is constructed to transmit burst format data over power line channel with impulsive noise and narrowband interferences. Fast code synchronization is acquired by digital matched filter and data decision is accomplished by sampling pulses. In order to examine the performance of the power line communication system, but error rate and packet loss rate are measured over the simulation channel with various noise sources. When the packet composed of 1-bit preamble and 63-bit data is transmitted under very high burst impulsive noise, the bit error rate is about 10$^3$-10$^4$ and the packet loss rate is below 0.07.

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A Systematic Method of Probing Channel Characteristics of Home Power Line Communication Network for IP Based Control of Home Appliances (IP기반 가전 제어를 위한 전력선 통신망 채널 특성 추정기법에 관한 연구)

  • Ahn, Nam-Ho;Kim, Jung-Keun;Lee, Jae-Sik;Chang, Tae-Gyu;Kim, Hoon
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.52 no.12
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    • pp.696-701
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    • 2003
  • This paper presents a systematic method of probing channel characteristics and communication reliabilities of home power line communication network applied to the Internet accessed control of home appliances. The effects of the three performance deterioating factors, i.e., additive noise, channel attenuation, and intersymbol interference, can be systematically measured by applying the channel probing waveform in the frequency range from 100KHz to 450KHz. Probability of bit error is derived with the probed channel parameters of the signal attenuation, noise and signal-to-interference ratio read in the frequency domain. The agreement between the derived probability of bit error and the measured probability of bit error supports the validity of the proposed approach of probing home power line channel characteristics. The experimental results performed with the constructed test-bed applying the proposed channel probing method also support the feasibility of commercially deploying the PLC modem installed home appliances and their services for the Internet accessed home automation.

64 Bit EISC Processor Design (64 Bit EISC 프로세서 설계)

  • 임종윤;이근택
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.161-164
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    • 2000
  • The architecture of microprocessor for a embedded system should be one that can perform more tasks with fewer instruction codes. The machine codes that high-level language compiler produces are mainly composed of specific ones, and codes that have small size are more frequently used. Extended Instruction Set Architecture (EISC) was proposed for that reason. We have designed pipe-line system for 64 bit EISC microprocessor. function level simulator was made for verification of design and instruction set architecture was also verified by that simulator. The behavioral function of synthesized logic was verified by comparison with the results of cycle-based simulator.

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Binary ASK way for 1Giga bit MODEM (1Giga bit MODEM을 위한 Binary ASK방식)

  • ;;;Sosuke Onodera;Yoichi Sato
    • Proceedings of the IEEK Conference
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    • 2003.07a
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    • pp.194-197
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    • 2003
  • We proposed Binary ASK system for 1Giga bit Modem. The Binary ASK system has a high speed shutter transmitter and no IF receiver only by symbol synchronization. The advantage of proposed system is that circuitry is very simple without IF process. The disadvantage of proposed system are that line spectrum occurs unordinary interference to other channels, and enhancement to 4-level system is impossible due to its large SNR degradation.

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Application of Computer-coupled Mass Spectrometer for Continuous On-line Monitoring of Cell Growth and Growth Rate (세포증식과 증식속도의 On-line Monitoring을 위한 Computer- coupled Mass Spectrometer의 응용)

  • 남수완;최춘순;김정회
    • Microbiology and Biotechnology Letters
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    • v.17 no.3
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    • pp.241-246
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    • 1989
  • Continuous on-line monitoring of cell concentration and growth rate in aerobic batch fermentation process was carried out by analyzing the exhaust gas composition of tormentor with a quadrupole mass spectrometer. From the mass spectrometric analyses of major gaseous components, i.e. $N_2$, $O_2$, $CO_2$ and $H_2O$, and the material balance equations for oxygen and carbon dioxide, oxygen uptake rate (OUR) rind carbon dioxide evolution rate (CER) were instantaneously calculated using a computer (16-bit IBM PC-AT) interfaced to a quadrupole mass spectrometer. The calculated OUR and CER data were used for the estimation of cell concentration and growth rate of Candida utilis during batch culture. It was found that the cell concentration could be satisfactorily estimated from the data of OUR arid CER during the culture and this method could be successfully und for the continuous monitoring of cell growth and growth rate.

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