• Journal of Broadcast Engineering
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• v.14 no.1
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• pp.70-80
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• 2009

We propose an ideal line coding for high speed data communication in visible light communication system. B4-HBT line coding is defined as follow. The 1 bit is +V at first though 1 encodes +Voltage and -Voltage doing change of shift each other, then -V newly. V that is been mutually contradictory for 1 bit that exist before that if continuous 0 bits exist 4 here same and reduces mistake because has reverse mark V in 4 continuous last 0 bits and gives half bit variation in 1 bit and made effect of noise low. 2${\sim}$3 dB profit is seen comparing with line coding that exist in simulation result.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.76-83
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• 2007

This paper describes a low power ROM using single charge-sharing capacitor and hierarchical bit line (SCSC-ROM). The SCSC-ROM reduces the power consumption in bit lines. It lowers the swing voltage of bit lines to a very small voltage by using a charge-sharing technique with a single capacitor. It implements the capacitor with dummy bit lines to improve noise immunity and make easy to design. The hierarchical bit line further saves the power by reducing the capacitance in bit lines. The SCSC-ROM also reduces the power consumption in control unit and predecoder by using the hierarchical word line decoder. The simulation result shows that the SCSC-ROM with $4K{\times}32bits$consumes only 37% power of a conventional ROM. A SCSC-ROM chip is fabricated in a $0.25{\mu}m$ CMOS process. It consumes 8.2mW at 240MHz with 2.5V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.2
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• pp.123-129
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• 2002

5-bit broadband MMIC phase shifter has been designed and fabricated. For the broadband performance, 11.25$^{\circ}$, 22.5$^{\circ}$, 45$^{\circ}$ and 90$^{\circ}$ bit have been designed with Lange coupler and 180$^{\circ}$ bit has been implemented by using shorted coupled line with Lange coupler and $\pi$-network of transmission line. Due to Lange coupler with large size, the Lange couplers have been folded far circuit size reduction. Low loss PIN diode has been utilized as a switch for each bit. Fabricated 5-bit broadband phase shifter shows the measured results that RMS phase error of 5 major phases is 3.5$^{\circ}$, maximum insertion loss is 12.5 dB, and maximum input and output return loss are 7 dB and 10 dB, respectively. The size of fabricated phase shifter is 6.5$\times$5.3 $ extrm{mm}^2$.

• Proceedings of the Korean Magnestics Society Conference
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• 2003.06a
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• pp.174-175
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• 2003

• Journal of the Korean Institute of Telematics and Electronics
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• v.16 no.1
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• pp.14-21
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• 1979

This paper deals with tIne interface error in the on-line computer systems by using the FSK radio communications. The wideband frequency shrift keying method is used for briary data transmission between the remote terminals and the main computer. To mintmize the error rate In the decoder systems of the main computer, a synchronizing pulse is added to the frame, so that the phase In both receiver and transmitter are synchronized. When the information signal with a constant error bit is received through FSK, It is designed to use the microprocessor for calculation of error bit. As results, most bit error are caused in FSK radio communications. and a few error bit Is me - asured to enter the mirroprocessor from the input buffer.

• ETRI Journal
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• v.26 no.6
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• pp.583-588
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• 2004

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.532-541
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• 2003

In a memory, most power is dissipated in high capacitive lines such as predecoder lines, word lines, and bit lines. To reduce the power dissipation in these high capacitive lines, this paper proposes three techniques using charge recycling and charge sharing. One is the charge recycling predecoder (CRPD). The second one is the charge recycling word line decoder (CRWD). The last one is the charge sharing bit line (CSBL) for a ROM. The CRPD and the CRWD recycle the previously used charge in predecoder lines and word lines. Theoretically, the power consumption in predecoder lines and word lines are reduced to a half. The CSBL reduces the swing voltage in the ROM bit lines to very small voltage using a charge sharing technique. the CSBL can significantly reduce the power dissipation in ROM bit lines. The CRPD, the CRWD, and the CSBL consume 82%, 72%, and 64% of the power of previous ROM designs respectively. A charge recycling and charge sharing ROM (CRCS-ROM) with the CRPD, the CRWD, and the CSBL is implemented. A CRCS-ROM with 8K16bits was fabricated in a 0.3${\mu}{\textrm}{m}$ CMOS process. The CRCS-ROM consumes 8.63㎽ at 100MHz with 3.3V. The chip core area is 0.1 $\textrm{mm}^2$.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.4
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• pp.169-176
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• 2010

We propose a Z-HBT line coding for a LED-ID system. Z-HBT line coding is defined as follows. First, we apply half bit transition to one bit. Second, we decode encoded bits using difference of bit transition level in one bit duration. As a result, we obtain advantages about synchronization problem and noise effect mitigation at the receiver. We set up outdoor the LED-ID simulation environment. At simulation results, we show 2-3dB gain as compared with existing line coding schemes. The results of the paper can be applied to design and implementation of LED-ID systems for indoor wireless multimedia services.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.63-67
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• 2003

This paper proposes a new BLSA(Bit Line Sense Amplifier) for MRAM. Current BLSA employs a latch-type circuit to amplify a signal from the selected memory cell. The proposed BLSA simplifies the circuit by amplifying the signal using cross-coupled PMOS transistors. It shows the same operation speedas the latch-type BLSA in simulation and occupies only 85% of the area taken by the latch-type BLSA.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.436-442
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• 2014

A new bus-invert coding circuit, called Two-bit Bus-Invert Coding (TBIC) is presented. TBIC partitions a bus into a set of two-bit sub-buses, and applies the bus-invert (BI) algorithm to each sub-bus. Unlike ordinary BI circuits using invert-lines, TBIC does not use an invert-line, so that it sends coding information through a bus-line. To transmit 3-bit information with 2 bus-lines, TBIC allows one bus-line to have a mid-level state, called M-state. TBIC increases the performance of BI algorithm, by suppressing the generation of overhead transitions. TBIC reduces bus transitions by about 45.7%, which is 83% greater than the maximum achievable performance of ordinary BI with invert-lines.