• Proceedings of the KIEE Conference
• /
• 2003.11b
• /
• pp.75-78
• /
• 2003

In this paper, a second-order 3-bit DSM using DWA(Data Weighted Averaging) algorithm is designed for bluetooth Zero-IF Receiver. The designed circuit has two integrators using a designed OTA, nonoverlapping two-phase clerk generator, 3-bit A/D converter, DWA algorithm and 3-bit D/A converter An ideal model of second-order lowpass DSM with a 3-bit quantizer was configured by using MATLAB, and each coefficients and design specification of each blocks were determined to have 10-bit resolution in 1MHz channel bandwidth. The designed second-order 3-blt lowpass DSM has maximum SNR of 74dB and power consumption is 50mW at 3.3V.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.105-108
• /
• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

• Proceedings of the KIEE Conference
• /
• 2006.04a
• /
• pp.81-83
• /
• 2006

This Paper suggests efficient design method which is used by Bit_Inerleaver in the IEEE 802.15,3.a. Bit_Interleaver is consist of Symbol_Interleaver and Tone_Interleaver Each Interleaver is designed by using memory. In other to resolve burst error, Block Interleaver is using different leading and writing address for mixing the data. However This method has a different reading and writing memory address to realize Block Interleaver so this schematic is some complex. This Paper suggests efficient and simple Bit_Interleaver Method which classify the memory of Bit_Interleavr to reduce complexity of shcemeatic.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.5
• /
• pp.18-24
• /
• 2011

In multibit Sigma-Delta Modulator, one of the DEM(Dynamic Element Matching) techniques which is DWA(Data Weighted Averaging) is widely used to get rid of non-linearity caused by mismatching of capacitor that is unit element of feedback DAC. In this paper, by adjusting clock timing used in existing DWA architecture, 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. After designing the 3rd 3-bit SC(Switched Capacitor) Sigma-Delta Modulator by using the proposed DWA architecture, 0.1% of mismatching into unit element in input frequency 20 kHz and sampling frequency 2.56 MHz. As a consequence of the simulation, It was able to get the same resolution as the existing architecture and was able to reduce the number of MOS Tr. by 222.

• Journal of Internet of Things and Convergence
• /
• v.9 no.3
• /
• pp.81-86
• /
• 2023

SSD (solid state disk), which is flash memory-based storage device, has the advantages of high density and fast data processing. Therefore, it is being utilized as a storage device for high-capacity data storage systems that manage rapidly increasing big data. However, flash memory, a storage media, has a physical limitation that when the write/erase operation is repeated more than a certain number of times, the cells are worn out and can no longer be used. In this paper, we propose a method for converting defective multi-bit cells into single-bit cells to reduce the defect rate of flash memory and extend its lifetime. The proposed idea distinguishes the defects and treatment methods of multi-bit cells and single-bit cells, which have different physical characteristics but are treated as the same defect, and converts the expected defective multi-bit cells into single-bit cells to improve the defect rate and extend the overall lifetime. Finally, we demonstrate the effectiveness of our proposed idea by measuring the increased lifetime of SSD through simulations.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.8
• /
• pp.17-22
• /
• 2007

In this paper, we propose a threshold estimation algorithm for a noncoherent IR-UWB receiver using 1-bit sampler. The proposed method reduces the hardware complexity by using the information of binary data resulted from 1-bit sampler instead of measuring the energy level of a received signal. Besides, mathematical modeling shows that the performances are similar to those of theoretically optimal threshold in terms of bit error rate. Computer simulations based on the IEEE 802.15.4a channel model also demonstrate the superiority of the proposed algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.6
• /
• pp.1-8
• /
• 2000

In this paper, design of sense amplifier for a flash memory minimizing bit line disturbance due to common bit line is presented. There is a disturbance problem at output modes by using common bit line, when the external devices access an internal flash memory. This phenomenon is resulted form hot carrier between floating gates and bit lines by thin oxide thickness. To minimize bit line disturbance, lower it line voltage is required and need sense amplifier to detect data existence in lower bit line voltage. Proposed circuits is operated at lower bit line voltage and we fabricated a embedded flash memory MCU using 0.6u technology.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.4B
• /
• pp.743-754
• /
• 2000

In this paper, we propose wavelet transform image compression method using shuffling and bit plane correlation. Proposed method is that original image decompose into multiresolutions using biorthogonal wavelet transform with linear phase response property and decomposed subbands are classified by maximum classification gain. And classified data sets in each subband are quantized using arbitrary set optimum bit allocation method. Quantized data sets in each subband are shuffled and context based bit plane arithmetic encoded .In context based bit plane arithmetic encoding, the context for each subband is not assigned uniformly, but assigned according to maximum correlation direction. Our results are comparable, or superior for some images at low rates, to published state-of-the-art coders.

• Progress in Superconductivity
• /
• v.6 no.1
• /
• pp.7-12
• /
• 2004

Due to the very fast switching speed of Josephson junctions, superconductive digital circuit has been a very good candidate fur future electronic devices. High-speed and Low-power microprocessor can be developed with Josephson junctions. As a part of an effort to develop superconductive microprocessor, we have designed an RSFQ 4-bit ALU (Arithmetic Logic Unit) in a pipelined structure. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in this work consisted of three DC current driven SFQ switches and a half-adder. We successfully tested the half adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached switches at the input ports to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this setup, 1-bit block of ALU was successfully tested up to 40 GHz. An RSFQ 4-bit ALU was fabricated and tested. The circuit worked at 5 GHz. The circuit size of the 4-bit ALU was 3 mm ${\times}$ 1.5 mm, fitting in a 5 mm ${\times}$ 5 mm chip.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.12 no.1
• /
• pp.47-52
• /
• 2017

This study is BIT(: Bus Information Terminal) features that take advantage of KEPCO eIoT(: energy Internet of Thing) platform, and it's Network configuration is composed of display terminal device, gateway, platform, and the service server. The key features are parts for processing protocol data between the gateway and the device using LoRa(: Long Range) technology, Intelligent applications and SIP(: Session Initiation Protocol) data handling connected to the Taxi reservation system. And the resource tree provided BIT for the service, which commonly used in the application server and the device.