• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(4)
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• pp.98-101
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• 2000

On CELP type Vocoders G.723.1 6.3kbps/5.3kbps Dual Rate Speech Codec, which is developed for Internet Phone and videoconferencing, uses VAD(Voice Activity Detection)/CNG (Comfort Noise Generator) in order to reduce the bit rate in a silence period. In order to reduce the bit rate effectively in this paper, we first set the boundary condition of the energy threshold to prevent the consumption of unnecessary processing time, and use three decision rules to detect an active frame by energy, pitch gain and LSP distance. To evaluate the performance of the proposed algorithm we use silence-inserted speech data with 0, 5, 10, 20dB of SNR. As a result when SNR is over 5dB, the bit rate is reduced up to about 40% without speech degradation and the processing time is additionally decreased.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제3권5호
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• pp.461-474
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• 2009

The cognitive radio (CR) technique is a useful tool for improving spectrum utilization by detecting and using the vacant spectrum bands in which cooperative spectrum sensing is a key element, while avoiding interfering with the primary user. In this paper, we propose a novel cluster-based cooperative spectrum sensing scheme in cognitive radio with two solutions for the purpose of improving in sensing performance. First, for the cluster header, we use the double adaptive energy thresholds and a multi-bit quantization with different quantization interval for improving the cluster performance. Second, in the common receiver, the weighed HALF-voting rule will be applied to achieve a better combination of all cluster decisions into a global decision.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1093-1096
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• 1998

The architecture and circuit design of low voltage, high performance barrel shifter is proposed in this paper. The proposed architecture consists of two arrays for byte and bit rotate/shift to perform 32-bit operation and is preferred for even bigger data length as it can be adapted for 64-bit extention with no increase of number of stages. NORA logic structure was used for circuit implementation to achieve the best performance in terms of speed, power and area. The complicated cloking control has been resolved with the ingenious design of clock dirver. The circuit simulation results in 3.05ns delay, 9.37㎽ power consumption at 1V, 160MHz operation when its implemented in low power $0.5\mu\textrm{m}$ CMOS technology.

• 한국정보통신학회논문지
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• 제10권12호
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• pp.2157-2165
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• 2006

항등 비트율 서비스를 위한 대표적인 이용자 트래픽 통제 알고리즘인 GCRA에 있어서 네트워크의 과부하와 전송 도중 불가피하게 발생하는 전송지연 변동에 따른 이용자 트래픽의 과도한 손실을 방지하기 위해서는 적절한 전송 지연변동 허용치의 설정이 매우 중요하다. 본 논문에서는 항등 비트율의 소스 트래픽에 대한 GCRA 순응검사에서 지연변동 허용치의 범 위에 따른 GCRA의 성능을 여러 측면에서 분석하고 적절한 지연변동 허용치 설정을 위한 가이드라인을 제시한다.

• 한국통신학회논문지
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• 제14권5호
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• pp.442-452
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• 1989

시스토릭 어레이를 이용한 FIR 필터를 구현하여 고속처리가 가능하게 설계하였으며, Cascade하게 칩연결이 가능하도록 설계하여 최대 128차의 FIR 필터를 실현할 수 있도록 하였다. 필터 계수는 Sign and Magnitude 형태로 외부에서 입력하며, 데이터는 2's Complement 형태로 입력되게 시스템을 설계하였다.

• ETRI Journal
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• 제29권6호
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• pp.820-822
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• 2007

ARIA and the Advanced Encryption Standard (AES) are next generation standard block cipher algorithms of Korea and the US, respectively. This letter presents an area-efficient unified hardware architecture of ARIA and AES. Both algorithms have 128-bit substitution permutation network (SPN) structures, and their substitution and permutation layers could be efficiently merged. Therefore, we propose a 128-bit processor architecture with resource sharing, which is capable of processing ARIA and AES. This is the first architecture which supports both algorithms. Furthermore, it requires only 19,056 logic gates and encrypts data at 720 Mbps and 1,047 Mbps for ARIA and AES, respectively.

• 대한전자공학회논문지
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• 제22권2호
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• pp.36-43
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• 1985

NMOS IC layout에서 직사각형 도형의 갯수에 비례하는 검사시간을 소모하는 설제규칙 검사의 알고리즘의 제안되고 그것에 의한 program이 개발 되었다. 일반적인 설계규칙 검사 algorithm의 시간소모는 0(nlogn) 혹은 0(n**1 . 2)에 비례하는데 반하여 (n은 직사각형 도형의 갯수) 이 논문에서는 pattern의 DF(direct format) data와 bit-map plane을 연관 지음으로써 0(n)에 비례하는 시간소모를 달성 할 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권2호
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• pp.141-146
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• 2002

The effect of the wide-bandgap Schottky barrier enhancement cap layer on the performance of metal-semiconductor-metal photodetectors (MSMPD's) is presented. Judged by the dc characteristics, no considerable increase in recombination loss of carriers is resulted by the incorporation of the cap layer. However, about 45% of the detection efficiency is lost for the cap-layered MSMPD's even with a graded layer incorporated under pulse operation, and it was found to be due mainly to the capturing and slow release of the photocarriers at the heterointerface. The loss mechanism of the pulse detection efficiency is believed to be responsible for the intersymbol interference and the increased bit-error-rate (BER) observed in MSMPD's when used with a high bit rate pseudo-random-bit-stream (PRBS) data pattern.

• International Journal of Internet, Broadcasting and Communication
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• 제5권2호
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• pp.11-14
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• 2013

This paper describes the sigma-delta ADC/DAC digital block with two channels. The ADC block has comb filter and three half band filters. And the DAC block has 5th Cascaded-of-Integrators Feedback DSM. The ADC and DAC support I2S, RJ, LJ and selectable input data modes of 24bit, 20bit, and 16bit. It is fabricated with 0.35um Hynix standard CMOS cell library. The chip size is 3700*3700um. It has been verified using NC Verilog Simulator and Matlab Tool.

• 한국통신학회논문지
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• 제16권1호
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• pp.13-22
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• 1991

본 논문에서는 단층 구조 퍼셉트론 신경 회로망 모델을 사용하여 입력 데이타에서 발생한 2비트의 에러를 검증 및 수정하는 회로를 설계하였다. 순회 해밍 부호를 응용하여 6비트의 데이타 비트와 8비트의 체크 비트를 갖는(14, 6) 블럭 부호를 사용하였다. 모든 회로들은 이중 배선 CMOS 2$\mu$m 설계 규칙에 따라 설계되었다. 회로를 시뮬레이션한 결과. 2비트 에러 검증 및 수정 회로는 최대 67MHz의 입력주파수에서 동작함을 확인하였다.