• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.192-195
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• 2000

GSM(Global System for Mobile Communication) system which is being used in Europe is composed A3, A5 and A8 algorithms. In this paper we implement A3 algorithm using VHDL, and verify the design by simulation. The A3 algorithm is divided into 3 parts, the encryption part, in which F-function encrypts 64 bit block data；the key generation part, which produces 32 bit subkeys；the control part, which produces the control code.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.97-100
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• 2001

A 3-way VLIW multimedia signal processor capable of efficient repeated operations as well as both load/store and type transformations for various data types is presented. It is composed of a 32-bit execution unit that can execute two instructions in parallel, an independent load/store unit and a control unit. The processor is implemented with 0.6${\mu}{\textrm}{m}$ gate array and the results are discussed.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.153-156
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• 2001

This paper describes a 12-bit high speed pipeline CMOS A/D converter. The A/D converter simulated the 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. The results show DNL and INL of $\pm$0.5LSB and $\pm$1.0LSB, conversion rate of 100Msamples/s, and power dissipation of 500㎽ with a power supply of 3.3V

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.733-736
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• 1999

In this Paper, Bit selectable and Bi-directional Interface Port is described, which can communicate data with the peripheral devices. Specially A description of the asynchronous design method is given to remove the clock skew phenomenon and the output asynchronous control method which finds the optimal clock and controls all the enable signal of the output pins at the same time is presented. Using this technique interface ports have delay time of less-than 0.5㎱.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.243-246
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• 2002

This paper presents a study on the design and implementation of modulized I/O buffer control system for large capacity cable check. A 8bit I/O buffer basic module which has feedback loops with input and output buffers is simulated in PSpice and implemented with logic gates. This system is composed of 18 sub-boards which have 3 channels of 32bit data buses, and of a main board with MPC860 microprocessor.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.156-158
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• 2006

A super-regenerative receiver is designed and tested at 433 MHz ISM band, The designed receiver has the data rate of up to 200 kbps and a power consumption of 10 mW. We carried out the system performance test for the TX power of 0.1 mW and 1 m distance. The result of the bit-error rate test shows one bit error among the 4000 bits.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.194-197
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• 1988

The unequal bit-error-probability of rate r=b/n binary convolutional code is analyzed. The error protection affored each digit of the b-tuple information word can be different from that afforded other digit. The property of the unequal protection can be applied to transmitting sampled data in PCM system.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.8
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• pp.15-21
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• 1996

This paper describes data placement schemes that provide uniform and balanced to multiple disks load for retrievals of VBR (variable bit rate) video at varying retrieval speeds. To support maximum concurent users at arbitrary-speed playbacks in a disk-arry based system, the hot spot disks should be carefully avoided. In this paper, we extend the proposed scheme, prime round-robin(PRR), for VBR video. In addition, we have compared the performance of PRR and PRR (PRR extension).

• Proceedings of the Korea Database Society Conference
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• 2000.11a
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• pp.280-286
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• 2000

본 논문에서는 기존의 비대화형 전송 프로토콜을 기반으로 하여 비밀정보교환을 위한 여러 가지 부가기능을 가지는 새로운 비대화형 전송 프로토콜을 설계 제안한다. 제안한 방식은 기존의 프로토콜의 구조를 그대로 따르면서 Bit Commitment 기법을 적용한 형태로서 여러가지 안전한 기능을 가진다. 본 논문에서 제안한 기법은 서로 신뢰하지 못하는 두 당사자 사이에서 비밀 정보를 교환하고자 하는 분야에 있어서 보다 안전한 프로토콜로서 활용될 수 있다.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.850-852
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• 2001

Fragile 워터마킹은 이미지의 무결성을 보장하기 위하여 원본 이미지에 사람이 지각할 수 없는 데이터를 삽입하는 것을 말한다. 본 논문은 이진 데이터의 삽입이 가능하며, 원본 이미지와 삽입된 데이터의 무결성이 보장되는 fragile 워터마킹의 한 방법을 제시한다. 제시된 방법은 hash 함수와 PRBG(pseudo random bit generator)를 이용한 one-time pad를 사용하며, 한 pixel당 약 2.8125bits의 정보를 저장할 수 있다.