• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.885-888
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• 2005

In this study, we designed an ARM9 compatible RISC microprocessor using VHDL. The microprocessor was designed to support Harvard architecture with separate instruction cache and data cache. The state machine was optimized for multi-cycle instructions. In addition, a data forwarding mechanism was adopted to reduce the stall cycles due to data hazards. Assembly programs were up-loaded into a ROM block for system-level simulation. Proper operation of the designed microprocessor was confirmed by investigating the contents of the internal registers as well as the RAM block. Futhermore, the simulation results clearly indicated that the operation speed of the processor designed in this study is enhanced by reducing the execution cycles required for multiplication related instructions.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.538-540
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• 2004

Electrical currents generated by human heart activities create magnetic fields represented by MCG(MagnetoCardioGram). Since an MCG signal acquisition system requires precise and stable operation, the system adopts hundreds of SQUID(Superconducting QUantum Interface Device) sensors for signal acquisition. Such a system requires fast real-time data acquisition in a required sampling interval, i.e., 1 mili-second for each sensor. This paper presents designed hardware to acquire data from 256-channel analog signal with 1 ksamples/sec speed, using 12-bit 8-channel ADC devices, SPI interfaces, parallel interfaces, 8-bit microprocessors, and a DSP processor. We implemented SPI interface between ADCs and a microprocessor, parallel interfaces between microprocessors. Our result concludes that the data collection can be done in $168{\mu}sec$ time-interval for 256 SQUID sensors, which can be interpreted to 6 ksamples/sec speed.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.632-634
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• 2004

First for high-qualify images and reducing process-error and driving speed, the designed 8-bit data driving circuit consists of a constant transconductance bias circuit, D-F/Fs by shift registers using static transmission gates, 1st latch and 2nd latch by tristate inverters, level shifters, current steering segmented D/A converters by 4MSB thermometer decoder and 4LSB weighted type. Second, we designed gray amp for power saving. These data driving circuits are designed with $0.35-{\mu}m$ CMOS technologies at 3.3 V and 18 V power supplies and simulated with HSPICE.

• Journal of Korean Institute of Industrial Engineers
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• v.41 no.4
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• pp.408-413
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• 2015

The quality prediction of the semiconductor industry has been widely recognized as important and critical for quality improvement and productivity enhancement. The main objective of this paper is to predict the final quality of semiconductor chips based on fail bit count information obtained from probe tests. Our proposed method consists of solving the data imbalance problem, non-parametric variable selection, and adjusting the parameters of the model. We demonstrate the usefulness and applicability of the proposed procedure using a real data from a semiconductor manufacturing.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.781-783
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• 1999

A storage or transmission of image is difficult without image compression processing because the numbers of generated or reborned image data are very much. In case of the random signal, image compression efficiency is low doing without loss of image information, but compressibility by using JPEG is better. We used Huffman code of JPEG, it assigne the low bit value for data of a lot of generated frequency, assigne the high bit value for data of a small quantity. This paper improved image compression efficiency with transformming Q-factor and certified the results with compressed image. A proposed method is very efficience for continuos a color tone image.

• Proceedings of the KSRS Conference
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• v.1
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• pp.267-270
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• 2006

COMS has two imaging payloads, MI (Meteorological Imager) and GOCI (Geostationary Ocean Colour Imager). In GOCI case, data are packaged per each slot - one part of 16 two-dimensional arrays for imaging sensors - so its generation algorithm is simple. But MI case, data are made up with sequences of 480 bit blocks and are transmitted to its ground station sequentially. Moreover there is no time information in each 480 bit MI block, so a system in its ground system should be attaching time information at received MI blocks. DM (Decomposition Module) is one module of IMPS that receives Raw Data from DATS and generates Level 0 Products that include time tagging. This paper explains DM design for MI of COMS payloads.

• Proceedings of the Polymer Society of Korea Conference
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• 2006.10a
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• pp.237-237
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• 2006

P(VDF/TrFE(72/28) ultrathin films were used in the fabrication of Metal-Ferroelectric polymer-Metal (MFM) single bit device with special emphasis on uniform film surface, faster dipole switching time under applied external field and longer memory retention time. AFM and FTIR-GIRAS were complementary in analyzing surface crystalline morphology and the resultant change in chain orientation with varying thermal history. DC-EFM technique was used to 'write-read-erase' the data on the memory bit in a much faster time than P-E studies. The results obtained from this study will enable us to have a good understanding of the ferroelectric and piezoelectric behavior of P(VDF/TrFE)(72/28) thin films suitable for high density data storage applications.

• Journal of information and communication convergence engineering
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• v.7 no.2
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• pp.152-156
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• 2009

This paper examines the BER performance of the recently proposed half-symbol-rate-carrier (HSRC) offset quadrature phase-shift-keying (OQPSK) receiver for high-speed data communication. A modified demodulation technique using a bit-time period signal integration, the bit-error-rate (BER) performance of the HSRC-OQPSK signal improves more than 4dB compared to that of a demodulation technique using a symbol-time period integration. This paper also examines the BER performance of modified demodulation with various band-limited channels modeled using low-pass filters, and the three different data-rate systems are simulated and compared with the performance of the system using the conventional demodulation technique.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.51-56
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• 2011

In this paper, we propose a CAN message compression method using bit rearrangement to reduce the CAN bus load and the error probability during the transmission of CAN messages. In conventional CAN message compression methods, message compression is accomplished by sending only the differences between the previous data and the current data. In the proposed method, the difference bits are rearranged to further increase the compression efficiency. By simulations in car applications, it is shown that the CAN transmission data is further reduced up to 26% by the proposed method, compared with the conventional method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.177-183
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• 2015

A high speed VLSI digital Winner-Take-All (WTA) circuit called simultaneous digital WTA (SDWTA) circuit is presented in this paper. A minimized comparison-cell (w-cell) is developed to reduce the size and to achieve high-speed. The w-cell which is suitable for VLSI implementation consists of only four transistors. With a minimized comparison-cell structure SDWTA can compare thousands of data simultaneously. SDWTA is scalable with O(mlog n) time-complexity for n of m-bit data. According to simulations, it takes 16.5 ns with $1.2V-0.13{\mu}m$ process technology in finding a winner among 1024 of 16-bit data.