• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.420-435
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• 2001

As multimedia technology has rapidly grown recently, many researches to process multimedia data efficiently using general-purpose processors have been studied. In this paper, we proposed multimedia instructions which can process multimedia data effectively, and suggested a processor architecture for those instructions. The processor was described with Verilog-HDL in the behavioral level and simulated with CADENCE$^{TM}$ tool. Proposed multimedia instructions are total 48 instructions which can be classified into 7 groups. Multimedia data have 64-bit format and are processed as parallel subwords of 8-bit 8 bytes, 16-bit 4 half words or 32-bit 2 words. Modeled processor is developed based on the Integer Unit of SPARC V.9. It has five-stage pipeline RISC architecture with Harvard principle.e.

• IEMEK Journal of Embedded Systems and Applications
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• v.15 no.4
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• pp.159-166
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• 2020

The IBC (Intra-Body Communication) benefits from a wireless communication system for exchanging various kinds of digital information through wearable electronic devices and sensors. The IBC using the human body as the transmission channel allows wireless communication without the transmitting radio frequency waves to the air. This paper discusses the results of experiments on electrostatic coupling IBC based on FSK (Frequency Shift Keying) and 1 bit error correction. We implemented FSK communication and 1 bit error correction algorithm using the MCU boards and aluminum tape electrodes. The transmitter modulates digital data using 50% duty square wave as carrier signal and transmits data through human body. The receiver performs ADC (Analog to Digital Conversion) on carrier signal from human body. In order to figure out the frequency of carrier signal from ADC results, we applied zero-crossing algorithm which is used to detect the edge characteristic in computer vision. Experiment results shows that digital data modulated as square wave can be successfully transmitted through human body by applying the proposed architecture of a 1ch GPIO as a transmitter and 1ch ADC for as a receiver. Also, this paper proposes 1 bit error correction technique for reliable IBC. This technique performs error correction by utilizing the feature that carrier signal has 50% duty ratio. When 1 bit error correction technique is applied, the byte error rate at receiver side is improved around 3.5% compared to that not applied.

• The Journal of the Acoustical Society of Korea
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• v.40 no.4
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• pp.359-369
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• 2021

In underwater communications, to compensate performance degradation induced from rapidly changing channel transfer characteristic, multi-band communication method which allocate the same data to different frequency bands is used. However, the multi-band configuration may have worse performance than the single-band one because performance degradation in a particular band affects the output from the entire bands. This problem can be solved through a receiving end that analyzes error rates of each band, sets threshold values and allocates lower weights to inferior bands. Therefore, this paper proposed a weighting algorithm based on estimated Bit Error Rate (BER) which analyzes reliability of received data based on the performance difference between demodulated and decoded data. Employing turbo codes with coding rate of 1/3, we evaluate the performance of the proposed weighted multi-band transmission model in real underwater environments based on optimal simulation parameters. Through the sea trial experiment, we confirmed error performance was improved by applying the proposed weighting algorithm.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.7
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• pp.305-317
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• 2008

As a mobile computing environment is rapidly changing, increasing user demand for multimedia-over-wireless capabilities on embedded processors places constraints on performance, power, and sire. In this regard, this paper proposes color media instructions (CMI) for single instruction, multiple data (SIMD) parallel processors to meet the computational requirements and cost goals. While existing multimedia extensions store and process 48-bit pixels in a 32-bit register, CMI, which considers that color components are perceptually less significant, supports parallel operations on two-packed compressed 16-bit YCbCr (6 bit Y and 5 bits Cb, Cr) data in a 32-bit datapath processor. This provides greater concurrency and efficiency for YCbCr data processing. Moreover, the ability to reduce data format size reduces system cost. The reduction in data bandwidth also simplifies system design. Experimental results on a representative SIMD parallel processor architecture show that CMI achieves an average speedup of 6.3x over the baseline SIMD parallel processor performance. This is in contrast to MMX (a representative Intel's multimedia extensions), which achieves an average speedup of only 3.7x over the same baseline SIMD architecture. CMI also outperforms MMX in both area efficiency (a 52% increase versus a 13% increase) and energy efficiency (a 50% increase versus an 11% increase). CMI improves the performance and efficiency with a mere 3% increase in the system area and a 5% increase in the system power, while MMX requires a 14% increase in the system area and a 16% increase in the system power.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.11-20
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• 1999

The data transfer width between the mocroprocessor and the memory comes to a critical part that limits system performance since the data transfer width has been as it was while the performance of a microprocessor is getting higher due to its continuous development in speed. And it is important that the memory should be in small size for the reduction of embedded microprocessor's price which is integrated on a single chip with the memory and IO circuit. In this paper, a mocroprocessor tentatively named as Extendable Instruction Set Computer(EISC) is proposed as the high code density 32 bit mocroprocessor architecture. The 32 bit EISC has 16 general purpose registers and 16 bit fixed length instruction which has the short length offset and small immediate operand. By using and extend register and extend flag, the offset and immediate operand could be extended. The proposed 32 bit EISC is implemented with an FPGA and all of its functions have been tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit EISC shows 140-220% and 120-140% higher code density than RISC and CISC respectively, which is much higher than any other traditional architectures. As a consequence, the EISC is suitable for the next generation computer architecture since it requires less data transfer width compared to any other ones. And its lower memory requirement will embedded microprocessor more useful.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.6
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• pp.592-598
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• 2000

The locality of data references at the distributed shared memory systems affects the performance significantly. Data allocation methods by considering the locality of data references can improve the performance of DSM systems. This paper evaluates the performance for the dynamic limited directory scheme which data allocation methods can apply very effectively. The information of the data allocation is used by the dynamic limited directory scheme to set the presence bit effectively. And the proper use of the presence bit improves the performance by reducing memory overhead and using directory pool efficiently. Simulations are conducted using three application programs which have various data sharing. The results show that the optimal data allocation method improves the performance up to 3.6 times in the proposed scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.3A
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• pp.406-411
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• 2000

In wireless ATM system, powerful FEC code is required for highly reliable data transmission. In this paper, we propose an adaptive hybrid ARQ scheme using RCPSCCC for WATM system. The code rate of RCPSCC is adjusted to match channel conditions and data types. By using only the effective free distances of outer and inner encoders, we derive upper bounds of the bit and word error probabilities over Rayleigh and Rician fading channels. By applying RCPSCC to the adaptive hybrid ARQ protocol, highly reliable data transmission can be achieved.

• ETRI Journal
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• v.35 no.1
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• pp.158-161
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• 2013

This letter proposes a low-power current-steering digital-to-analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in which the data will not be changed. The 10-bit DAC is implemented using a $0.13-{\mu}m$ CMOS process with $V_{DD}$=1.2 V. Its area is $0.21\;mm^2$. It consumes 4.46 mW at a 1-MHz signal frequency and 200-MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25-MHz and 10-MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1-MHz and 50-MHz signal frequencies, respectively.

• ETRI Journal
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• v.35 no.1
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• pp.166-169
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• 2013

In this letter, we propose a data randomization scheme for endurance and interference mitigation of deeply-scaled multilevel flash memory. We address the relationships between data patterns and the raw bit error rate. An on-chip pseudorandom generator composed of an address-based seed location decoder is developed and evaluated with respect to uniformity. Experiments performed with 2x-nm and 4x-nm NAND flash memory devices illustrate the effectiveness of our scheme. The results show that the error rate is reduced up to 86% compared to that of a conventional cycling scheme. Accordingly, the endurance phenomenon can be mitigated through analysis of interference that causes tech shrinkage.

• Journal of the East Asian Society of Dietary Life
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• v.14 no.2
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• pp.135-144
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• 2004

A total of 40 Korean and Japanese rice varieties were evaluated for their main chemical components, physical properties, cooking quality, pasting properties, and instrumental measurements. Based on their quality evaluations, it was concluded that Korean and Japanese rice varieties were not significantly different in the basic components of NIR (Near Infra Red) data and the chemical analysis from the uncooked brown and milled rices. Korean rice had a little bit higher protein and amylose contents but much lower fat acidity than those of Japanese rice from the chemical analysis. From all the data of three different kinds of NIR methods, Korean and Japanese milled rice were very similar except the taste score. Japanese rice showed a slightly higher taste score, a little bit higher lightness and whiteness, but lower yellowness and redness than Korean one. From all those data of NIR and the chemical analysis, Korean and Japanese rices had very similar components except the fat content.