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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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10-Bit 200-MS/s Current-Steering DAC Using Data-Dependant Current-Cell Clock-Gating

  • Yang, Byung-Do (Department of Electronics Engineering, Chungbuk National University) ;
  • Seo, Bo-Seok (Department of Electronics Engineering, Chungbuk National University)
  • Received : 2012.06.27
  • Accepted : 2012.08.02
  • Published : 2013.02.01
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Abstract

This letter proposes a low-power current-steering digital-to-analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in which the data will not be changed. The 10-bit DAC is implemented using a $0.13-{\mu}m$ CMOS process with $V_{DD}$=1.2 V. Its area is $0.21\;mm^2$. It consumes 4.46 mW at a 1-MHz signal frequency and 200-MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25-MHz and 10-MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1-MHz and 50-MHz signal frequencies, respectively.

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References

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