• Progress in Superconductivity
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• 제7권2호
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• pp.109-113
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• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.

• 전자공학회논문지CI
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• 제47권5호
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• pp.10-16
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• 2010

XML은 점점 데이터 교환과 정보 관리에서 중요하게 여겨진다. 따라서 XML 문서들을 접근, 질의, 저장하는 효율적인 방법들을 개발하기 위한 많은 노력이 진행되고 있다. 본 논문은 XML 문서들을 효율적으로 군집화 하는 새로운 기법을 제안한다. XML 문서를 군집화하기 위해 문서를 대표하는 비트 벡터를 제안한다. 두 XML 문서의 유사도는 대응하는 두 비트 벡터간의 bit-wise AND 연산에 의해서 측정된다. 실험 결과 XML 문서의 특징으로 비트 벡터가 사용되었을 때 군집화가 제대로 그리고 효율적으로 형성됨을 알 수 있다.

• 정보저장시스템학회논문집
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• 제6권1호
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• pp.31-36
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• 2010

Data storage related with writing and retrieving requires high storage capacity, fast transfer rate and less access time. Today any data storage system cannot satisfy these conditions, however holographic data storage system can perform faster data transfer rate because it is a page oriented memory system using volume hologram in writing and retrieving data. System can be constructed without mechanical actuating part so fast data transfer rate and high storage capacity about 1Tb/cm3 can be realized. In this research, to correct errors of binary data stored in holographic data storage system, a new method for reduction errors is suggested. First, find cluster centers using subtractive clustering algorithm then reduce intensities of pixels around cluster centers. By using this error reduction method following results are obtained ; the effect of Inter Pixel Interference noise in the holographic data storage system is decreased and the intensity profile of data page becomes uniform therefore the better data storage system can be constructed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.145-148
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• 2000

A 16bit asynchronous multiplier has been designed using micropipelind structure with 2 phase and data bundling. And 4-radix modified Booth algorithm, CPlatch(Cature-Pass latch) and modified 4-2 counters have adopted in this design. It is implemented in 0.65$\mu\textrm{m}$ double-poly/double-metal CMOS technology by using 12,074 transistors with core size of 1.4${\times}$1.8$\textrm{mm}^2$. And our design results in a computation rate 55MHz a supply voltage of 3.3V.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
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• pp.165-168
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• 2000

The bit error rate(BER)of the data passed through Wideband-Code Division Multiple Access (W-CDMA) system with turbo-codes structure is presented. The performance of turbo-codes under W-CDMA system is estimated for various users and iteration numbers of decoding. The channel model is Additive White Gaussian Noise(AWGN) and Rayleigh fading channel. When iteration number increases, bit error probability of turbo-codes decreases. and when the number of users increase, bit error probability of turbo-codes increases.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2006년도 가을 학술발표논문집 Vol.33 No.2 (C)
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• pp.313-316
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• 2006

네비게이션 시스템, PDA, DMB단말기, 휴대폰 등과 같이 모바일 단말기가 보편화 되면서 이 시스템을 유지하기 위한 데이터베이스 관리시스템의 수요가 증가하고 있다. 이러한 모바일 단말기는 기존의 데이터베이스 관리 시스템과는 달리 공간적인 소형화와 에너지 소비량을 최소화 해야 한다. 본 논문은 두 가지에 중점을 두어 결합 비트(combined bit)데이터 타입을 제안하고 구현방법을 제시했다. 결합 비트를 사용함으로써 저장 공간의 절약, 검색 속도 향상, 구성비트 복합 검색의 효율적 지원, 결합 비트의 도입으로 질의의 편리성의 이점이 있다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅳ
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• pp.1791-1794
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• 2003

In this Paper, we propose a new watermarking algorithm for 1-bit image authentication using block operation. Observing 3${\times}$3 block patterns, we find the regions to watermark, We describe a specific scheme how to generate data to embed and find pixels most probably invisible under modifications. We also show the experimental results of proposed algorithm.

• 대한전자공학회논문지SD
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• 제46권11호
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• pp.84-91
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• 2009

본 논문은 multi-level signaling을 이용한 high speed serial link transmitter에 관하여 제안하였다. High speed serial link에서 수 Gb/s를 달성하기 위해 4-pulse amplitude modulation (PAM) 을 사용하였다. 4-PAM은 4개의 level로 한 symbol time에 2 bit data를 전송함으로써 binary signaling보다 2배 빠른 data 전송이 가능해졌다. 제안된 4-PAM transmitter는 전압 output 대신 전류 output을 생성하며 이로 인해 driver의 switching time이 빨라져서 더 높은 속도의 transmitter를 구현할 수 있었다. $2^5-1$ pseudo-random bit sequence (PRBS) 생성기는 built-in self test (BIST)를 하기 위해 on-chip으로 설계되었다. 본 연구는 동부 하이텍 $0.18{\mu}m$ CMOS 공정을 통하여 설계되었으며 1.8 V supply voltage에서 eye 크기가 160 mV 이고 최대 동작 속도는 8 Gb/s이다. 칩 전체 면적은 $0.7\times0.6mm^2$이며 전력 소모는 98 mW이다.

• 정보저장시스템학회논문집
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• 제3권2호
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• pp.94-112
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• 2007

Nano-sized inverted domain dots in ferroelectric materials have potential application in ultrahigh-density rewritable data storage systems. Herein, a data storage system is presented based on scanning non-linear dielectric microscopy and a thin film of ferroelectric single-crystal lithium tantalite. Through domain engineering, we succeeded to form an smallest artificial nano-domain single dot of 5.1 nm in diameter and artificial nano-domain dot-array with a memory density of 10.1 Tbit/$inch^2$ and a bit spacing of 8.0 nm, representing the highest memory density for rewritable data storage reported to date. Sub-nanosecond (500psec) domain switching speed also has been achieved. Next, long term retention characteristic of data with inverted domain dots is investigated by conducting heat treatment test. Obtained life time of inverted dot with the radius of 50nm was 16.9 years at $80^{\circ}C$. Finally, actual information storage with low bit error and high memory density was performed. A bit error ratio of less than $1\times10^{-4}$ was achieved at an areal density of 258 Gbit/inch2. Moreover, actual information storage is demonstrated at a density of 1 Tbit/$inch^2$.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 B
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• pp.1295-1297
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• 1996

CCITT G.721, G.723 standard ADPCM algorithm is implemented by using TI's fixed point DSP start kit (DSK). ADPCM can be implemented on a various rates, such as 16K, 24K, 32K and 40K. The ADPCM is sample based compression technique and its complexity is not so high as the other speech compression techniques such as CELP, VSELP and GSM, etc. ADPCM is widely applicable to most of the low cost speech compression application and they are tapeless answering machine, simultaneous voice and fax modem, digital phone, etc. TMS320C50 DSP is a low cost fixed point DSP chip and C50 DSK system has an AIC (analog interface chip) which operates as a single chip A/D and D/A converter with 14 bit resolution, C50 DSP chip with on-chip memory of 10K and RS232C interface module. ADPCM C code is compiled by TI C50 C-compiler and implemented on the DSK on-chip memory. Speech signal input is converted into 14 bit linear PCM data and encoded into ADPCM data and the data is sent to PC through RS232C. The ADPCM data on PC is received by the DSK through RS232C and then decoded to generate the 14 bit linear PCM data and converted into the speech signal. The DSK system has audio in/out jack and we can input and out the speech signal.