• Title/Summary/Keyword: bipolar transistor

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Estimation of Insulated-gate Bipolar Transistor Operating Temperature: Simulation and Experiment

  • Bahun, Ivan;Sunde, Viktor;Jakopovic, Zeljko
    • Journal of Power Electronics
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    • v.13 no.4
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    • pp.729-736
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    • 2013
  • Knowledge of a power semiconductor's operating temperature is important in circuit design and converter control. Designing appropriate circuitry that does not affect regular circuit operation during virtual junction temperature measurement at actual operating conditions is a demanding task for engineers. The proposed method enables virtual junction temperature estimation with a dedicated modified gate driver circuit based on real-time measurement of a semiconductor's quasi-threshold voltage. A simulation was conducted before the circuit was designed to verify the concept and to determine the basic properties and potential drawbacks of the proposed method.

Analysis of the Electrical Characteristics with Channel Length in n-ch and p-ch poly-Si TFT's (채널 길이에 따른 n-채널과 p-채널 Poly-Si TFT's의 전기적 특성 분석)

  • Back, Hee-Won;Lee, Jea-Huck;Lim, Dong-Gyu;Kim, Young-Ho
    • Proceedings of the KIEE Conference
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    • 1999.11d
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    • pp.971-973
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    • 1999
  • 채널길이에 따른 n-채널과 p-채널 poly-Si TFT's를 제작하고 그 전기적 특성을 분석하였다. n-채널과 p-채널소자는 공통적으로 기생바이폴라트 랜지스터현상(parasitic bipolar transistor action)에 의한 kink 효과, 전하공유(charge sharing)에 의한 문턱전압의 감소, 소오스와 드레인 근처의 결함에 의한 RSCE(reverse short channel effect) 효과, 수직전계에 의한 이동도의 감소, 그리고 avalanche 증식에 의한 S-swing의 감소가 나타났다. n-채널은 p-채널 보다 더 큰 kink, 이동도, S-swing의 변화가 나타났으며, 높은 드레인 전압에서의 문턱전압의 이동은 avalanche 증식(multiplication)에 의한 것이 더 우세한 것으로 나타났다. 누설전류의 경우, 채널 길이가 짧아짐에 따라 n-채널은 큰 증가를 나타냈으나 p-채널의 경우는 변화가 나타나지 않았다.

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Analytical Assessment on the Cooling Structure of In-wheel Driving Inverter (인휠 모터 구동용 인버터의 냉각구조에 대한 해석적 평가)

  • Kim, Sung Chul
    • Transactions of the Korean Society of Automotive Engineers
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    • v.22 no.2
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    • pp.1-6
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    • 2014
  • In-wheel driving inverter inside engine room sometimes operates in the harsh environment like high temperature of about $105^{\circ}C$. Especially, the size and power density of the inverter has become smaller and more increased. Thus, it is essential to manage the temperature of the inverter with IGBT (Insulated Gate Bipolar Transistor) switching devices for performance and endurance, because the temperature can be getting increase. In this paper, we performed the thermal flow analysis of inverter models with wave type and pin fin type cooling channels, and investigated the heat transfer characteristics of the inverter models using cooling water on channels at 8 L/min and $65^{\circ}C$. Also, we compared the thermal performance under various conditions such as coolant flow rate and layered power module structure. Therefore, we determined the feasibility of the initial inverter models and the thermal performance enhancement.

DEVELOPMENT OF INTELLIGENT POWER UNIT FOR HYBRID FOUR-DOOR SEDAN

  • Aitaka, K.;Hosoda, M.;Nomura, T.
    • International Journal of Automotive Technology
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    • v.4 no.2
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    • pp.57-64
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    • 2003
  • The Intelligent Power Unit (IPU) utilized in Honda's Civic Hybrid Integrated Motor Assist (IMA) system was developed with the aim of making every component lighter, more compact and more efficient than those in the former model. To reduce energy loss, inverter efficiency was increased by fine patterning of the Insulated Gate Bipolar Transistor (IGBT) chips, 12V DC-DC converter efficiency was increased by utilizing soft-switching, and the internal resistance of the IMA battery was lowered by modifying the electrodes and the current collecting structure. These improvements reduced the amount of heat generated by the unit components and made it possible to combine the previously separated Power Control Unit (PCU) and battery cooling systems into a single system. Consolidation of these two cooling circuits into one has reduced the volume of the newly developed IPU by 42% compared to the former model.

Numerical Analyses on Snapback-Free Shorted-Anode SOI LIGBT by using a Floating Electrode and an Auxiliary Gate (플로우팅 전극과 보조 게이트를 이용하여 스냅백을 없앤 애노드 단락 SOI LIGBT의 수치 해석)

  • O, Jae-Geun;Kim, Du-Yeong;Han, Min-Gu;Choe, Yeon-Ik
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.49 no.2
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    • pp.73-77
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    • 2000
  • A dual-gate SOI SA-LIGBT (shorted-anode lateral insulated gate bipolar transistor) which eliminates the snapback effectively is proposed and verified by numerical simulation. The elimination of the snapback in I-V characteristics is obtained by initiating the hole injection at low anode voltage by employing a dual gate and a floating electrode in the proposed device. For the proposed device, the snapback phenomenon is completely eliminate, while snapback of conventional SA-LIGBT occurs at anode voltage of 11 V. Also, the drive signals of two gates have same polarity by employing the floating electrode, thereby requiring no additional power supply.

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A New Snap-back Suppressed SA-LIGBT with Gradual Hole Injection (점진적인 홀의 주입을 통해 스냅백을 억제한 새로운 구조의 SA-LIGBT)

  • Jeon, Jeong-Hun;Lee, Byeong-Hun;Byeon, Dae-Seok;Lee, Won-O;Han, Min-Gu;Choe, Yeol-Ik
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.49 no.2
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    • pp.113-115
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    • 2000
  • The gradual hole injection LIGBT (GI-LIGBT) which employs the dual gate and the p+ injector, was fabricated for eliminating a negative resistance regime and reducing a forward voltage drop in SA-LIGBT. The elimination of the negative resistance regime is successfully achieved by initiating the hole injection gradually. Furthermore, the experimental results show that the forward voltage drop of GI-LIGBT decreases by lV at the current density of 200 $A/cm^2$, when compared with that of the conventional SA-LIGBT. It is also found that the improvement in the on-state characteristics can be obtained without sacrificing the inherent fast switching characteristics of SA-LIGBT.

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A Study on the Characteristics of PSA Device using RTA Process and Trench Technology (RTA 공정 및 Trench 격리기술을 사용한 PSA 바이폴라 소자의 특성 연구)

  • Koo, Yong-Seo;Kang, Sang-Won;An, Chul
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.28A no.9
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    • pp.743-751
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    • 1991
  • This paper presents the 1.5\ulcorner PSA bipolar device which establishes the performance improvement such as the reduction of emitter resistance and substrate junction capacitance. To achieve the above electrical characteristics, RTA process and trench isolation technology were adapted. The emitter resistance and substrate capacitance of npn transistor having 1.5$[\times}6{\mu}m^{2}$emitter area was measured with 63$\Omega$and 28fF, respectively. The minimum propagation delay time shows 121ps at 0.7mW from the measurement of 31 stage ring oscillator.

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Mixed-Mode Simulation of the Power MOSFET with Current Limiting Capability (전류 제한 능력을 갖는 전력용 MOSFET의 Mixed-Mode 시뮬레이션)

  • Yun, Chong-Man;Choi, Yearn-Ik;Han, Min-Koo
    • Proceedings of the KIEE Conference
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    • 1994.07b
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    • pp.1451-1453
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    • 1994
  • A monolithic current limiting power MOSFET, which may be easily fabricated by the conventional DMOS process, is proposed. The proposed current limiting MOSFET consists of main power cells, sensing cells, and NPN lateral bipolar transistor so that users can adjust the current limiting levels with only one external resistor. The behaviors of the proposed device are numerically simulated and analyzed by 2-D device simulator MEDICI and mixed-mode simulator CA-AAM(Circuit Analysis Advanced Application Module).

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Design of Gate-Ground-NMOS-Based ESD Protection Circuits with Low Trigger Voltage, Low Leakage Current, and Fast Turn-On

  • Koo, Yong-Seo;Kim, Kwang-Soo;Park, Shi-Hong;Kim, Kwi-Dong;Kwon, Jong-Kee
    • ETRI Journal
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    • v.31 no.6
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    • pp.725-731
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    • 2009
  • In this paper, electrostatic discharge (ESD) protection circuits with an advanced substrate-triggered NMOS and a gate-substrate-triggered NMOS are proposed to provide low trigger voltage, low leakage current, and fast turn-on speed. The proposed ESD protection devices are designed using 0.13 ${\mu}m$ CMOS technology. The experimental results show that the proposed substrate-triggered NMOS using a bipolar transistor has a low trigger voltage of 5.98 V and a fast turn-on time of 37 ns. The proposed gate-substrate-triggered NMOS has a lower trigger voltage of 5.35 V and low leakage current of 80 pA.

수배전 시스템의 에너지 절약$\cdot$이용합리화 3. 액티브 콘덴서

  • 대한전기협회
    • JOURNAL OF ELECTRICAL WORLD
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    • s.264
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    • pp.84-89
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    • 1998
  • 지금까지 수전설비의 역률조정에는 진상콘덴서가 사용되었고 콘덴서뱅크의 투입-해별에 따라 Step 모양으로 제어하여, 역률 개선효과는 0.98$\~$0.97정도가 일반적이었다.그러나 자에너지(에너지 절약$\cdot$이용합리화)에 대한 관심이 높아지는 가운데, 부하기기에 대해서는 파워일렉트로닉스 기술을 이용한 인버터화 등에 의하여 자에너지화가 도모되고 있다. 또한 코제너레이션의 설치에 의한 설비 전체로서의 에너지의 유효활동도 이루어져, 역률조정에서도 변동이 적고 가능한 한 고역률을 유지할 것을 요망하고 있다. 또 자에너지화에 크게 기여하고 있는 인버터 등에서 발생하는 전기공해라고도 할 수 있는 고조파전류가 많이 발생하고, 이 고조파전류의 유입으로 진상콘덴서의 과열$\cdot$이음발생 등의 이상을 일으키는 경우가 최근에 많이 발생하고 있다. 이와 같은 배경에서 액티브필터 제어기술을 적용하여 전력용콘덴서를 사용하지 않는 무효전력보상장치인 액티브 콘덴서(active condenser)를 제품화하여 시장에 내놓았다. 액티브 콘덴서는-무효전류 연속제어에 의하여 전원역률을 1.0으로 유지 -고속응답성 -대용량 IGBT(Insulted Gate Bipolar transistor)소자의 채용에 의한 소형화 -고조파의 영향을 받지 않음 등 지금까지의 진상콘덴서에는 없는 우수한 장점이 있어, 자에너지와 고조파문제에 유효한 수단이 되고 있다.

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