• 전자공학회논문지A
• /
• 제30A권10호
• /
• pp.41-50
• /
• 1993

This paper describes the fabrication process and electrical characteristics of PSA (Polysilicon Self-Align) bipolar transistors with a thin base width of 1100.angs.. To realize this shallow junction depth, one-step rapid thermal annealing(RTA) technology has been applied instead of conventional furnace annealing process. It has been shown that the series resistances and parasitic capacitances are significantly reduced in the device with emitter area of 1${\times}4{\mu}m^{2}$. The switching speed of 2.4ns/gate was obtained by measuring the minimum propagation delay time in the I$^{2}$L ring oscillator with 31 stages.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제7권4호
• /
• pp.274-280
• /
• 2007

This paper demonstrates an efficiency improvement of the class E power amplifier (PA) by tuning-out the input capacitance ($C_{IN}$) of the power HBT with a shunt inductance. In order to obtain high output power, the PA needs the large emitter size of a transistor. The larger the emitter size, the higher the parasitic capacitance. The parasitic $C_{IN}$ affects the distortion of the voltage signal at the base node and changes the duty cycle to decrease the PA's efficiency. Adopting the L-C resonance, we obtain a remarkable efficiency improvement of as much as 7%. This PA exhibits output power of 29 dBm and collector efficiency of 71% at 1.9 GHz.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
• /
• pp.692-696
• /
• 1997

본 연구에서는 BJT(Bipolar Junction Transistor)와 MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 등을 1MeV에너지의 전자빔을 선량을 변화시켜가며 조사시켜 그 특성 변화를 분석하였다. BJT에 대해서는 조사 전, 후의 전류 이득의 측정을 통해 base 에서의 minority-carrie의 수명 변화에 의해서 전류 이득이 감소하는 것으로 나타났으며, MOSFET의 경우는 oxide 지역의 전하량 변화에 의해서 문턱 전압이 영향을 받음을 확인할 수 있었다. BJT의 minority-carrier의 수명 감소량은 조사 선량이 증가함에 따라 직선적으로 변화함을 알 수 있었고, MOSFET의 문턱 전압의 변화는 nMOS와 pMOS의 경우 서로 다름을 관찰할 수 있었는데 이는 oxide내에서 발생하는 전하에 의해 차이가 남을 알 수 있었다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2006년도 추계학술대회 논문집 전기물성,응용부문
• /
• pp.97-98
• /
• 2006

High current behaviors of extended drain n-type metal-oxide-semiconductor field effects transistor (EDNMOS) with double polarity source (DPS) for electrostatic discharge (ESD) protection are analyzed. Simulation based contour analyses reveal that combination of bipolar junction transistor operation and deep electron channeling induced by high electron injection gives rise to the second on-state. Therefore, the deep electron channel formation needs to be prevented in order to realize stable and robust ESD protection performance. Based on our analyses, general methodology to avoid the double snapback and to realize stable ESD protection is to be discussed.

• ETRI Journal
• /
• 제27권4호
• /
• pp.449-452
• /
• 2005

The electrical characteristics of solid state devices such as the bipolar junction transistor (BJT), metal-oxide semiconductor field-effect transistor (MOSFET), and other active devices are altered by impinging photon radiation and temperature in the space environment. In this paper, the threshold voltage, the breakdown voltage, and the on-resistance for two kinds of MOSFETs (200 V and 100 V of $V_{DSS}$) are tested for ${\gamma}-irradiation$ and compared with the electrical specifications under the pre- and post-irradiation low dose rates of 4.97 and 9.55 rad/s as well as at a maximum total dose of 30 krad. In our experiment, the ${\gamma}-radiation$ facility using a low dose, available at Korea Atomic Energy Research Institute (KAERI), has been applied on two commercially available International Rectifier (IR) products, IRFP250 and IRF540.

• 대한전기학회논문지
• /
• 제45권2호
• /
• pp.230-234
• /
• 1996

A new trenched Hybrid Schottky INjection Field Effect Transistor (HSINFET) is proposed and verified by 2-D semiconductor device simulation. The feature of the proposed structure is that the hybrid Schottky injector is implemented at the trench sidewall and p-n junction injector at the upper sidewall and bottom of a trench. Two-dimensional simulation has been performed to compare the new HSINFET with the SINFET, conventional HSINFET and lateral insulated gate bipolar transistor(LIGBT). The numerical results shows that the current handling capability of the proposed HSINFET is significantly increased without sacrificing turn-off characteristics. The proposed HSINFET exhibits higher latch-up current density and much faster switching speed than the lateral IGBT. The forward voltage drop of the proposed HSINFET is 0.4 V lower than that of the conventional HSINFET and the turn-off time of the trenched HSINFET is much smaller than that of LIGBT.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2002년도 추계학술대회 논문집 전기물성,응용부문
• /
• pp.141-144
• /
• 2002

The method of the analysis of the base Gummel number of the PNP BJT(Bipolar Junction Transistor) for integrated circuits based upon the semiconductor physics is proposed and the method of calculating the doping profile of the base region using process conditions is presented. The transistor saturation current obtained from the proposed method of PNP BJT using 20V and 30V process shows an averaged relative error of 6.7% compared with the measured data.

• Journal of Power Electronics
• /
• 제13권4호
• /
• pp.729-736
• /
• 2013

Knowledge of a power semiconductor's operating temperature is important in circuit design and converter control. Designing appropriate circuitry that does not affect regular circuit operation during virtual junction temperature measurement at actual operating conditions is a demanding task for engineers. The proposed method enables virtual junction temperature estimation with a dedicated modified gate driver circuit based on real-time measurement of a semiconductor's quasi-threshold voltage. A simulation was conducted before the circuit was designed to verify the concept and to determine the basic properties and potential drawbacks of the proposed method.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2000년도 하계학술대회 논문집
• /
• pp.55-58
• /
• 2000

SiGe heterojuction bipolar transistors (HBT) have been studied and applied for advanced high speed integrated circuits. Device characteristics of SiGe HBT depending on the Ge profile of the transistor base region have been analysed using a device simulator, ATLAS/BLAZE. The models and parameters have been calibrated to the measured characteristics of the device, having a trapeziodal base profile, including the cut-off frequency of 45GHz and the dc current gain of 200. The Ge concentration which increases linearly, exponentially, or root-functionally from the emitter-base junction to the base-collector junction, has been tried to find out the influence on the device characteristics. The cut-off frequency and gain rather strongly depends on the exponential and root-functional Ge base profiles, respectively.

• 대한전자공학회논문지SD
• /
• 제41권7호
• /
• pp.7-12
• /
• 2004

본 논문에서는 교류전류 집중현상이 고려된 바이폴라 등가모델에서 내부 베이스-컬렉터 캐패시턴스(C/sub μ/)와 외부 베이스-컬렉터 캐패시턴스(C/sub μx/)를 분리해서 추출하는 개선된 방법을 연구하였다. 먼저, 기존 추출방법들의 문제점들을 파악하고, 교류전류 집중 캐패시턴스가 포함된 차단모드 등가회로로부터 개선된 추출방정식들을 유도하였다. 이렇게 추출된 C/sub μx/와 C/sub μx/를 사용하여 모델 된 전류 및 전력이득 주파수 응답곡선들은 기존 추출방법으로 얻어진 곡선보다 측정 데이터와 훨씬 잘 일치되었으며, 이는 개선된 추출방법의 정확도를 증명한다.