• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.23-30
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• 2012

This paper proposes a novel adaptive header-based power gating structure to compensate for the performance loss and the increased wake-up time of the power gating structures induced by the negative bias temperature instability (NBTI) effect. The proposed structure consists of variable width footers based on the two-pass power gating and a new NBTI sensing circuit for an adaptive control. The simulation results of the proposed structure are compared to those of power gating without the adaptive control and show that both the circuit-delay and wake-up time dependence of the power gating structure on the NBTI stress is minimized with only 3% and 4% increase, respectively while keeping small leakage power and rush-current. In this paper, a 45 nm CMOS technology and predictive NBTI model have been used to implement the proposed circuits.

• 전자공학회논문지 IE
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• v.44 no.2
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• pp.1-7
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• 2007

The increasing high frequency capabilities of CMOS have resulted in increased RF and analog design in CMOS. Design of RF and analog circuits depends critically on device S-parameter characteristics, magnitude of real and imaginary components and their behavior as a function of frequency. Utilization of scaled high performance CMOS technologies poses challenges as concerns for reliability degradation mechanisms increase. It is important to understand and quantify the effects of the reliability degradation mechanisms on the S-parameters and in turn on small signal model parameters. Various physical effects influencing small-signal parameters, especially the transconductance and capacitances and their degradation dependence, are discussed in detail. The measured S-parameters of H-gate and T-gate devices in a frequency range from 0.5GHz to 40GHz. All intrinsic and extrinsic parameters are extracted from S-parameters measurements at a single bias point in saturation. In this paper we discuss the analysis of the small signal equivalent circuits of RF SOI MOSFET's verificated for the purpose of exacting the change of parameter of small signal equivalent model followed by device flame.

• Journal of the Korean Operations Research and Management Science Society
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• v.29 no.3
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• pp.41-61
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• 2004

The purpose of this paper is to construct $\ulcorner$CIDEAR(Cross Impact-DEA-AR)$\lrcorner$ model which evaluates proposed R&D projects considering cross impact among them and selects proper projects to utilize resources efficiently as well as to maximize efficacy of investments. For this purpose, $\ulcorner$CIDEAR$\lrcorner$ model is designed as the following six steps. $\ulcorner$Decision Theory Evaluation Model$\lrcorner$ is for setting and selecting the evaluation items according to the structured procedure of evaluation system. The priority of items is decided at $\ulcorner$AR Decision Model$\lrcorner$$\ulcorner$Cross Impact Estimation Model$\lrcorner$ is for computing the final probability of success and the result is used to revise the evaluation results of $\ulcorner$Decision Theory Evaluation Model$\lrcorner$. $\ulcorner$Resource Performance Analysis Model$\lrcorner$ classifies the proposed R&D projects on the basis of required resources and expected performance. Consequently, the possibility of bias of project selection can be prevented. $\ulcorner$Priority Oder Decision Model$\lrcorner$ is for computing the efficacy of proposed projects. Finally, $\ulcorner$Efficacy-Efficiency Cause Analysis Model$\lrcorner$ analyzes the structure of efficacy and efficiency of the projects. The major findings and significances of this study are summarized as follows: (1) $\ulcorner$CIDEAR$\lrcorner$ model can deal with the affairs of R&D projects having the characteristics of mutual independence as well as mutual dependence in the point of efficacy and efficiency. Hence, it is possible to evaluate and select R&D projects more accurately. (2) It can be possible to raise the possibility of projects success. R&D manager can use the information for project management because the efficacy-efficiency structure of selected projects can be analyzed. (3) We proved the usefulness of the constructed $\ulcorner$CIDEAR$\lrcorner$ model using an case about twenty-one R&D projects of a leading company of electronic industry in Korea.

• Korean Journal of Remote Sensing
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• v.29 no.6
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• pp.631-644
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• 2013

Significant Wave Height (SWH) data measured by satellite altimeters (Topex/Poseidon, Jason-1, Envisat, and Jason-2) were validated in the seas around Korea by comparison with wave height measurements from marine meteorological buoy stations of Korea Meteorological Administration (KMA). A total of 1,070 collocation matchups between Ku-band satellite altimeter data and buoy data were obtained for the periods of the four satellites from 1992 to the present. In the case of C-band and S-band observations, 1,086 matchups were obtained and used to assess the accuracy of satellite SWH. Root-Mean-Square (RMS) errors of satellite SWH measured with Ku-band were evaluated to roughly 0.2_2.1 m. Comparisons of the RMS errors and bias errors between different frequency bands revealed that SWH observed with Ku-band was much more accurate than other frequencies, such as C-band or S-band. The differences between satellite SWH and buoy wave height, satellite minus buoy, revealed some dependence on the magnitude of the wave height. Satellite SWH tended to be overestimated at a range of low wave height of less than 1 m, and underestimated for high wave height of greater than 2 m. Such regional characteristics imply that satellite SWH should be carefully used when employed for diverse purposes such as validating wave model results or data assimilation procedures. Thus, this study confirmed that satellite SWH products should be continuously validated for regional applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.832-835
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• 2001

We report the structural and electrical properties of hafnium oxide (HfO$_2$) films with tungsten silicide (WSi$_2$) metal gate. In this study, HfO$_2$thin films were fabricated by oxidation of sputtered Hf metal films on Si, and WSi$_2$was deposited directly on HfO$_2$by LPCVD. The hysteresis windows in C-V curves of the WSi$_2$HfO$_2$/Si MOS capacitors were negligible (<20 mV), and had no dependence on frequency from 10 kHz to 1 MHz and bias ramp rate from 10 mV to 1 V. In addition, leakage current was very low in the range of 10$^{-9}$ ~10$^{-10}$ A to ~ 1 V, which was due to the formation of interfacial hafnium silicate layer between HfO$_2$and Si. After PMA (post metallization annealing) of the WSi$_2$/HfO$_2$/Si MOS capacitors at 500 $^{\circ}C$ EOT (equivalent oxide thickness) was reduced from 26 to 22 $\AA$ and the leakage current was reduced by approximately one order as compared to that measured before annealing. These results indicate that the effect of fluorine diffusion is negligible and annealing minimizes the etching damage.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.123-129
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• 1996

LDD structure is widely accepted in fabricating short channel MOSFETs due to reduced short channel effect originated form lower drain edge electric field. However, modeling of the LDD device is troublesome because the analysis methods of LDD region known are either too complicated or inaccurate. To solve the problem, this paper presents a nonlinear resistance model for the LDD region based on teh fact that the electron mobility changes with positive gate bias because accumulation layer of electrons is formed at the surface of the LDD region. To prove the usefulness of the model, single source/drain and LDD nMOSFETs were fabricated with 0.35$\mu$m CMOS technolgoy. For the fabricated devices we have measured I$_{ds}$-V$_{gs}$ characteristics and compare them to the modeling resutls. First of all, we calculated channel and LDD region mobility from I$_{ds}$-V$_{gs}$ characteristics of 1050$\AA$ sidewall, 5$\mu$m channel length LDD NMOSFET. Then we MOSFET and found good agreement with experiments. Next, we use calculated channel and LDD region mobility to model I$_{ds}$-V$_{gs}$ characteristics of LDD mMOSFET with 1400 and 1750$\AA$ sidewall and 5$\mu$m channel length and obtained good agreement with experiment. The single source/drain device characteristic modeling results indicates that the cahnnel mobility obtained form our model in LDD device is accurate. In the meantime, we found that the LDD region mobility is governed by phonon and surface roughness scattering from electric field dependence of the mobility. The proposed model is useful in device and circuit simulation because it can model LDD device successfully even though it is mathematically simple.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.348-354
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• 2009

It has analyzed that the device degradation by NBTI (Negative Bias Temperature Instability) stress induced the increase of gate-induced-drain-leakage(GIDL) current for p-MOSFETs. It is shown that the degradation magnitude, as well as its time, temperature, and field dependence, is govern by interface traps density at the silicon/oxide interface. from the relation between the variation of threshold voltage and subthreshold slope, it has been found that the dominant mechanism for device degradation is the interface state generation. From the GIDL measurement results, we confined that the EHP generation in interface state due to NBTI stress led to the increase of GIDL current. Therefore, one should take care of the increased GIDL current after NBTI stress in the ultra-thin gate oxide device. Also, the simultaneous consideration of reliability characteristics and dc device performance is highly necessary in the stress engineering of nanoscale CMOSFETs.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.6
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• pp.48-56
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• 1989

Contact-type linear image sensors for facsimile have been fabricated by means of rf glow discharge decomposition method of silane. The dependence of their electrical and optical properties on rf power, $SiH_4$ flow rate, ambient gas pressure, $H_2SiH_4$ ratio and substrate temperature are described. The a-Si:H monolayer demonstriated photosensitivity of 0.85 and $I_{ph}/I_d$ ratio of 100 unger 100 lux illumination. However, this monolayer has relatively high dark current due to carrier injection from both electrodes, resulting in low $I_{ph}/I_{dd}$ ratio. To suppress the dark current we have fabricated $SiO_2/i-a-Si:H/p-a-Si:H:B$ multilayer film with blocking structure. The photocurrent of this multilayer sensor with 6 V bias became saturated ar about 20nA under 10 lux illumination, while the dark current was less than 0.2 nA. Moreover, the spectral sensitivity of the multilayer film was enhanced for short wavelength visible region, compared with that of the a-Si:H monolayer. These results show that the fabricated photocon-ductive film can be used as the linear image sensor of the facsimile.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.335-340
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• 2002

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4${\AA}$ and 814${\AA}$, which have the gate area $10^3cm^2$. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.492-499
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• 2013

We have investigated the electrical properties of Ru/Ni/n-GaN Schottky structure using current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. The barrier height (${\Phi}_{bo}$) and ideality factor (n) of Ru/Ni/n-GaN Schottky structure are found to be 0.66 eV and 1.44, respectively. The ${\Phi}_{bo}$ and the series resistance ($R_S$) obtained from Cheung's method are compared with modified Norde's method, and it is seen that there is a good agreement with each other. The energy distribution of interface state density ($N_{SS}$) is determined from the I-V measurements by taking into account the bias dependence of the effective barrier height. Further, the interface state density $N_{SS}$ as determined by Terman's method is found to be $2.14{\times}10^{12}\;cm^{-2}\;eV^{-1}$ for the Ru/Ni/n-GaN diode. Results show that the interface state density and series resistance has a significant effect on the electrical characteristics of studied diode.