• Molecules and Cells
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• v.27 no.5
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• pp.497-502
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• 2009

In mouse embryos, somite formation occurs every two hours, and this periodic event is regulated by a biological clock called the segmentation clock, which involves cyclic expression of the basic helix-loop-helix gene Hes7. Hes7 expression oscillates by negative feedback and is cooperatively regulated by Fgf and Notch signaling. Both loss of expression and sustained expression of Hes7 result in severe somite fusion, suggesting that Hes7 oscillation is required for proper somite segmentation. Expression of a related gene, Hes1, also oscillates by negative feedback with a period of about two hours in many cell types such as neural progenitor cells. Hes1 is required for maintenance of neural progenitor cells, but persistent Hes1 expression inhibits proliferation and differentiation of these cells, suggesting that Hes1 oscillation is required for their proper activities. Hes1 oscillation regulates cyclic expression of the proneural gene Neurogenin2 (Ngn2) and the Notch ligand Delta1, which in turn lead to maintenance of neural progenitor cells by mutual activation of Notch signaling. Taken together, these results suggest that oscillatory expression with short periods (ultradian oscillation) plays an important role in many biological events.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3A
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• pp.237-246
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• 2007

Clock Synchronization is one of the most basic factors to be considered when we implement an indoor synchronization network for indoor positioning. In this paper, we present a new synchronization algorithm which does not employ time stamps in order to reduce the hardware complexity and data overhead. In addition to that, we describe an algorithm that is designed to compensate the frequency drift giving an serious impact on the synchronization performance. The performance evaluation of the proposed algorithm is achieved by investigating MTIE (Maximum Time Interval Error) values through simulations. In the simulations, the frequency drift values of the practical oscillators are used. From the simulation results, it is investigated that we can achieve the synchronization performance under 10 ns when we use 1 second synchronization interval with 1 ns resolution and TCXOs (Tmperature Compensated Cristal Oscillators) both in the master clock and the slave clock.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.405-414
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• 2016

IC-implementations provide high performance for solving the high computational cost of pattern matching but have relative low flexibility for satisfying different applications. In this paper, we report an associative memory architecture for k nearest neighbor (KNN) search, which is one of the most basic algorithms in pattern matching. The designed architecture features reconfigurable vector-component parallelism enabled by programmable switching circuits between vector components, and a dedicated majority vote circuit. In addition, the main time-consuming part of KNN is solved by a clock mapping concept based weighted frequency dividers that drastically reduce the in principle exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. A test chip in 180 nm CMOS technology, which has 32 rows, 8 parallel 8-bit vector-components in each row, consumes altogether in peak 61.4 mW and only 11.9 mW for nearest squared Euclidean distance search (at 45.58 MHz and 1.8 V).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.135-139
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• 2008

In this paper, tunable SC(switched capacitor) 2nd order bandpass $\Sigma-\Delta$(Sigma-Delta) modulator with novel architecture that can adjust the IF band center frequency by one coefficient value is proposed for data conversion in the IF(Intermediate Frequency) band. Its architecture can optionally adjust all the 2nd order noise transfer function in comparison with the conventional architecture. In order to adjust the center frequency, the conventional architecture needs the two variable coefficient values, basic clock and eight clocks. On the other hand, the proposed architecture can adjust the center frequency by one variable coefficient value and basic clock only.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1288-1291
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• 2002

In this paper, we present a design of mpeg-4 video codec chip to reduce the power consumption using frame level clock gating and motion estimation skip scheme. It performs 30 grames/s of codec (encoding and decoding) mode with quarter-common intermediate format(QCIF) at 27MHz. A novel low-power techniques were implemented in architectural level, which is 35% of the power dissipation for a conventional CMOS design. This chip performs MPEG-4 Simple Profile Level 2(Simple@L2) and H.263 base mode. Its contains 388,885 gates, 662k bits memory, and the chip size was 9.7 mm x 9.7 mm which was fabricated using 0.35 micron 3-layers metal CMOS technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.785-787
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• 2005

In the Bluetooth specification version 1.0, one specific frequency in one piconet was created depending upon the device clock and the Bluetooth native address at one specific time slot in the frequency hopping method. The basic hopping pattern was arranging the 79 ISM frequency band in pseudo-random fashion. Possible problem is the chance of collision of ownership of one specific frequency by more than 2 wireless devices when they are within the communication-active range. In this paper, we propose the adaptive frequency hopping method in order to resolve the possible problem so that more than 2 wireless devices communicates with their own client devices without being interfered. The proposed method was implemented with HDL later to be synthesized with an automatic EDA synthesizer and verified as well. The implemented adaptive frequency hopping circuit operated normally at 24MHz which will be the target clock frequency of the target Bluetooth device.

• ETRI Journal
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• v.25 no.6
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• pp.510-516
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• 2003

In this paper, we describe the development of a platform-based SoC of a 32-bit smart card. The smart card uses a 32-bit microprocessor for high performance and two cryptographic processors for high security. It supports both contact and contactless interfaces, which comply with ISO/IEC 7816 and 14496 Type B. It has a Java Card OS to support multiple applications. We modeled smart card readers with a foreign language interface for efficient verification of the smart card SoC. The SoC was implemented using 0.25 ${\mu}m$ technology. To reduce the power consumption of the smart card SoC, we applied power optimization techniques, including clock gating. Experimental results show that the power consumption of the RSA and ECC cryptographic processors can be reduced by 32% and 62%, respectively, without increasing the area.

• Journal of Veterinary Clinics
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• v.18 no.4
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• pp.324-328
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• 2001

This study was performed to evaluate the effects of $AS_2O_3$ upon antiangiogenesis in rat cornea, to examine it\`s possible application as an anticancer drug and to provide basic data for further studies of antiangiogenetic mechanism of $AS_2O_3$ . Angiogenesis was induced by cornea micropocket assay, as previously described. Sixteen of forty-eight eyes of Sprague-Dawley rats were randomly assigned to one of three groups, namely, only a bFGF group(control group), and a group treated by $AS_2O_3$ ($AS_2O_3$ group). After pellet implantation, we measured the number of new vessels, vessel length and clock hour of neovascularization, and area of neovascularization was determined using a mathematical formula. New vessels growing began at day 3, number of vessels in $AS_2O_3$ group were significantly more less than those in control group (p<0.05). The length of vessels of $AS_2O_3$ group was significantly shorter than that of control group after day 3(p<0.05). The clock hours of all group were slowly increased at all days but $AS_2O_3$ group was inhibited more than control group. Neovascularization areas of $AS_2O_3$ group were more significantly inhibited than those of control group (p<0.05). This study showed that $AS_2O_3$ had powerful antiangiogenetic effects and it would be useful in the choice of anticancer drug.

• ETRI Journal
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• v.25 no.6
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• pp.489-502
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• 2003

This paper presents an MPEG-4 video codec, called MoVa, for video coding applications that adopts 3G-324M. We designed MoVa to be optimal by embedding a cost-effective ARM7TDMI core and partitioning it into hardwired blocks and firmware blocks to provide a reasonable tradeoff between computational requirements, power consumption, and programmability. Typical hardwired blocks are motion estimation and motion compensation, discrete cosine transform and quantization, and variable length coding and decoding, while intra refresh, rate control, error resilience, error concealment, etc. are implemented by software. MoVa has a pipeline structure and its operation is performed in four stages at encoding and in three stages at decoding. It meets the requirements of MPEG-4 SP@L2 and can perform either 30 frames/s (fps) of QCIF or SQCIF, or 7.5 fps (in codec mode) to 15 fps (in encode/decode mode) of CIF at a maximum clock rate of 27 MHz for 128 kbps or 144 kbps. MoVa can be applied to many video systems requiring a high bit rate and various video formats, such as videophone, videoconferencing, surveillance, news, and entertainment.

• Proceedings of the IEEK Conference
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• 2000.06c
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• pp.121-124
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• 2000

Goal of this Paper is to design and develop core kernel components f3r single processor real-time system, which include real-time schedulers, synchronization mechanism, IPC, message passing, and clock & timer. The goal also contains the basic researches on dynamic load balancing and scheduling which provide mechanism for the distributed information processing and efficient resource sharing among various information appliances based on network.