• ETRI Journal
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• v.9 no.1
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• pp.118-124
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• 1987

Short channel n-MOSFET의 드레인-소오스 사이의 breakdown은 단순한 접합 breakdown이 아닌 avalanche-induced breakdown으로 p-MOSFET, long channel n-MOSFET의 breakdown 전압보다 훨씬 작은 값을 갖는다. Short channel n-MOSFET의 breakdown의 특징은 current-controlled 부저항 특성(snapback)이 나타나고, 게이트 전압에 따라 breakdown 전압보다 작은 sustainning 전압이 존재한다. 이와 같은 sustainning 전압은 short channel n-MOSFET의 안정한 동작에 또 하나의 제한 요소가 될 수 있다. 따라서 공정 및 회로 시뮬레이션을 위해, short channel n-MOSFET의 avalanche breakdown 현상에 대한 정확한 분석이 요구된다. Short channel n -MOSFET의 avalanche breakdown 현상을 분석하기 위해서Parasitic bipolar transistor를 도입한 분석적 모델을 이용하였다.

• Journal of the Semiconductor & Display Technology
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• v.6 no.3
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• pp.47-53
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• 2007

Ultra thin Si p-n junctions shallower than $300{\AA}$ were fabricated and biased to the avalanche regime. The ultra thin junctions were fabricated to be parallel to the surface and exposed to the surface without $SiO_2$ layer. Those junctions emitted white light and electrons when junctions were biased in the avalanche breakdown regime. Therefore, we could observe the avalanche breakdown region visually. We could also observe the influence of electric field to the current flow visually by observing the white light which correspond to the avalanche breakdown region. Arrayed diodes emit light and electrons uniformly at the diode area. But, the reverse leakage current were larger than those of ordinary diodes, and the breakdown voltage were less than 10V.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.232.2-232.2
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• 2013

본 연구에서는 asymmetric과 symmetric MOSFET 소자의 drain breakdown 및 snapback 특성을 분석하였다. 실험에서는 두 MOSFET 소자의 동작 영역에서 게이트와 드레인에 각각 전압을 인가하였다. 드레인 전류-전압 곡선으로 부터 drain breakdown 전압과 snapback 전압을 추출하였다. 결과 avalanche breakdown 발생 전의 드레인 전류는 asymmetric 구조의 경우 더 작은 값을 보였으며 이는 asymmetric 구조에서의 drain field 가 더 낮기 때문이다. 따라서 impact ionization은 asymmetric 구조에서 덜 발생하며, snapback 전압은 avalanche breakdown voltage가 작은 asymmetric 구조에서 크게 나타났다.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.9
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• pp.956-963
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• 1990

The general shapes of prebreakdown pulses in a discharge gap were calculated and the current pulses due to avalanche were detected in SF6 by changing the polarity of the protrusion placed on an electrode at pressures up to about 400 Kpa. The mathematical model of prebreakdown pulse development with a negative protrusion shows agreement with the observed pulses. No evidence of intense bursts of field-emitted electrons was observed. Breakdown probably results from a single avalanche developing to a critical size. However the calculated shape of prebreakdown current pulse does not agree with the observed pulses with a positive protrusion. The breakdown is preceded by multiple avalanche development at pressures less than about 200 Kpa. This observation has been interpreted as due to the formation of negative ions following photoionization in the gas which drift into the critical volume near a positive protrusion.

• Nuclear Engineering and Technology
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• v.56 no.8
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• pp.3076-3083
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• 2024

In this work, single photon avalanche diodes (SPADs) were fabricated using the standard 180 nm complementary metal-oxide semiconductor process. Their small size of 15-16 µ m and low operating voltage made it possible to easily integrate them with readout circuits for compact on-chip sensors, particularly those used in the radiation sensor network of a nuclear plant. Four architectures were proposed for the SPADs, with a shallow trench isolation (STI) guard ring and different depletion regions designed to demonstrate the main performance parameters in each experimental configuration. The wide absorption region structure with PSD and a deep N-well could achieve a uniform electric field, resulting in a stable dark count rate (DCR). Additionally, the STI guard ring was implanted to mitigate the premature edge breakdown. A breakdown voltage was achieved for a low operating voltage of 10.75 V. The DCR results showed 286.3 Hz per ㎛² at an excess voltage of 0.04 V. A photon detection probability of 21.48% was obtained at 405 nm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.206-209
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• 2002

With the progress of semiconductor processing technology, avalanohe photodiodes (APDs) based on InP/InGaAs are used for high-speed optical receiver modules. Planar-type APDs give higher reliability than mesa-type APDs. However, Planar-type APDs are struggled with a problem of intensed electric field at the junction curvature, which causes edge breakdown phenomena at the junction periphery. In this paper, we focused on studying the effects of junction curvature for APDs performances by different etching processes followed by single diffusion to from p-n junction. The performance of each process is characterized by observing electric field profiles and carrier generation rates. From the results, it can be understood to predict the optimum structure, which can minimize edge breakdown and improve the manufacturability.

• ETRI Journal
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• v.43 no.5
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• pp.916-922
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• 2021

We calculated the correlation between the doping concentration of the charge layer and the multiplication layer for separate absorption, grading, charge, and multiplication InGaAs/InAlAs avalanche photodiodes (APDs). For this purpose, a predictable program was developed according to the concentration and thickness of the charge layer and the multiplication layer. We also optimized the design, fabrication, and characteristics of an APD for 20 Gbps application. The punch-through voltage and breakdown voltage of the fabricated device were 10 V and 33 V, respectively, and it was confirmed that these almost matched the designed values. The 3-dB bandwidth of the APD was 10.4 GHz, and the bit rate was approximately 20.8 Gbps.

• Journal of information and communication convergence engineering
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• v.16 no.1
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• pp.43-47
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• 2018

The existing modeling of avalanche dominated breakdown in double gate MOSFETs (DGMOSFETs) is not relevant for 10 nm gate lengths, because the avalanche mechanism does not occur when the channel length approaches the carrier scattering length. This paper focuses on the punch through mechanism to analyze the breakdown characteristics in 10 nm DGMOSFETs. The analysis is based on an analytical model for the thermionic-emission and tunneling currents, which is based on two-dimensional distributions of the electric potential, obtained from the Poisson equation, and the Wentzel-Kramers-Brillouin (WKB) approximation for the tunneling probability. The analysis shows that corresponding flat-band-voltage for fixed threshold voltage has a significant impact on the breakdown voltage. To investigate ambiguousness of number of dopants in channel, we compared breakdown voltages of high doping and undoped DGMOSFET and show undoped DGMOSFET is more realistic due to simple flat-band-voltage shift. Given that the flat-band-voltage is a process dependent parameter, the new model can be used to quantify the impact of process-parameter fluctuations on the breakdown voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.299-302
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• 2001

In this study, we are studied the electrical conduction and dielectric breakdown properties of insulating varnish. In order to analyze the molecular structure and physical properties of insulating varnishs, FT-lR was used. As the result, it can be confirmed that the peak of alcoholic group appeared in wavenumbers 3452[cm$\^$-1], the peak of =CH appeared in 3080[cm$\^$-1] and the peak of -CH appeared in 2919[cm$\^$-1] respectively. The following results were obtained from electrical properties of insulating varnish. The amplitude of current density was decreased by thickness increasing and the current density was effected by the thermal energy from external due to temperature increasing. In study temperature dependence of dielectric strength, the specimen of 10[$\mu\textrm{m}$] thickness was measurement from room temperature to 180[$^{\circ}C$]. It is confirmed that the temperature regions below 60[$^{\circ}C$] is due to electron avalanche breakdown and the temperature regions over 60[$^{\circ}C$] is due to free volume breakdown which makes electron movements easy.

• Journal of IKEEE
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• v.26 no.3
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• pp.333-340
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• 2022

Process and device simulations were performed to determine the optimal ion implantation conditions to prevent double snapback of high voltage operating DDDNMOS (double diffused drain N-type MOSFET) device for ESD protection. By examining the effects of HP-Well, N^- drift and N⁺ drain ion implantation on the double snapback and avalanche breakdown voltages, it was possible to prevent double snapback and improve the electrostatic protection performance. If the ion implantation concentration of the N^- drift region rather than the HP-Well region is optimally designed, it prevents the transition from the primary on-state to the secondary on-state, so that relatively good ESD protection performance can be obtained. Since the concentration of the N^- drift region affects the leakage current and the avalanche breakdown voltage, in the case of a process technology with an operating voltage greater than 30V, a new structure such as DPS or colligation of optimal process conditions can be applied. In this case, improved ESD protection performance can be realized.