• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.6
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• pp.243-249
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• 2010

In this thesis, in order to a equivalent circuit-analytical study for a symmetric double gate type MOSFET, we slove analytically the 2D Poisson's equation in a a silicon body. To solve the threshold voltage in a symmetric double gate type MOSFET from the derived expression for the surface potential which the two-dimensional potential distribution of a symmetric double gate type MOSFET is assumed approximately. This thesis can use short and long channel in a silicon body we introduce a new the threshold voltage model in a symmetric double gate type MOSFET and measure it the distance about the range of channel length up to 0.1 [${\mu}m$].

• Transactions of the Korean Society of Automotive Engineers
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• v.11 no.2
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• pp.89-95
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• 2003

We consider a problem of application of analytical redundancy to engine synchronization process of spark ignition engines, which is critical to timing for every ECU process including ignition and injection. The engine synchronization process we consider here is performed using the pulse signal obtained by the revolution of crankshaft trigger wheel (CTW) coupled to crank shaft. We propose a discrete-time linear model for the signal, for which we construct FDI (Fault Detection & Isolation) system consisting residual generator and threshold based on linear observer.

• Smart Structures and Systems
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• v.14 no.2
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• pp.129-144
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• 2014

In this paper, a fuzzy inference system and an analytical hierarchy process-based online evaluation technique is developed to monitor the condition of the 32-km Donghai Bridge in Shanghai. The system has 478 sensors distributed along eight segments selected from the whole bridge. An online evaluation subsystem is realized, which uses raw data and extracted features or indices to give a set of hierarchically organized condition evaluations. The thresholds of each index were set to an initial value obtained from a structure damage and performance evolution analysis of the bridge. After one year of baseline monitoring, the initial threshold system was updated from the collected data. The results show that the techniques described are valid and reliable. The online method fulfills long-term infrastructure health monitoring requirements for the Donghai Bridge.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.869-872
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• 2006

In this paper, the threshold voltage roll-off been analyzed for nano structure double gate FinFET. The analytical current model has been developed , including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics are used to calculate thermionic emission current, and WKB(Wentzel- framers-Brillouin) approximation to tunneling current. The threshold voltage roll-offs are obtained by simple adding two currents since two current is independent. The threshold voltage roll-off by this model are compared with those by two dimensional simulation and two values are good agreement. Since the tunneling current increases especially under channel length of 10nm, the threshold voltage roll-off Is very large. The channel and gate oxide thickness have to be fabricated as thin as possible to decrease this short channel effects and this process has to be developed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.145-150
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• 2013

This paper has presented the analysis for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET as next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function has been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold characteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering are changed, and the deviation rate is changed for device parameters for DGMOSFET.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.760-765
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• 2007

In this paper, the threshold voltage roll-off and drain induced barrier lowering(DIBL) have been analyzed for nano structure double gate FinFET. The analytical current model has been developed, including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics were used to calculate thermionic omission current, and WKB(Wentzel- Kramers-Brillouin) approximation to tunneling current. The threshold voltage roll-offs are obtained by simple adding two currents since two current is independent. The threshold voltage roll-off by this model are compared with those by two dimensional simulation and two values are good agreement. Since the tunneling current increases especially under channel length of 10nm, the threshold voltage roll-off and DIBL are very large. The channel and gate oxide thickness have to be fabricated as thin as possible to decrease this short channel effects, and this process has to be developed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1648-1653
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• 2006

In this paper, transport characteristics have been investigated using analytical current-voltage model for double gate MOSFET(DGMOSFET). Scaling down to 100nm of gate length for MOSFET can bring about various problems such as a threshold voltage roll-off and increasing off current by tunneling since thickness of oxide is down by 1.fnm and doping concentration is increased. A current-voltage characteristics have been calculated according to changing of channel length,using analytical current-voltage relation. The analytical model has been verified by calculating I-V relation according to changing of oxide thickness and channel thickness as well as channel length. A current-voltage characteristics also have been compared and analyzed for operating temperature. When gate voltage is 2V, it is shown that a current-voltage characteristic in 77K is superior to in room temperature.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.683-685
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• 2012

This paper have presented the analysis of the change for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET with two gates to be next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold chatacteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering is changed, and the deviation rate is changed for device parameters for DGMOSFET.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.1-7
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• 2011

In this work, an analytical models for the threshold voltage and flat band voltage have been suggested and proved using 3-dimensional device simulator. The method for device design guideline and its example in nanowire junctionless transistor and example of device design of was also presented. One can find that the suggested model for threshold voltage and flat band voltage agrees with 3-dimension simulation results. The threshold voltage and flat band voltage are decreased with the increase of nanowire radius, gate oxide thickness, and channel impurity doping concentration. When the work function of gate material and the ratio of ON and OFF current is given, the device design guide line for nanowire junctionless transistor has been proposed. It is known that the device with high impurity channel concentration can be fabricated with th decreased of nanowire radius and gate oxide thickness.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.228-239
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• 2004

In this paper, an analytical model accounting for the quantum effects in MOSFETs has been developed to study the behaviour of $high-{\kappa}$ dielectrics and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and $I_D-V_D$ characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achieve targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.