• ETRI Journal
• /
• v.32 no.6
• /
• pp.911-920
• /
• 2010

This paper presents a method of designing hybrid analog/asymmetrical square-root (SR) FIR filters. In addition to the conventional frequency domain constraints, the proposed method considers time-domain constraints as well, including the inter-symbol interference (ISI) and the opening of the eye pattern at the receiver output. This paper also reviews a systematic way to find the discrete-time equivalence of analog parts in a band-limited digital communication system. Thus, a phase equalizer can be easily realized to compensate for the nonlinear phase responses of the analog components. With the hybrid analog/SR FIR filter co-design, examples show that using the proposed method can result in a more robust ISI performance in the presence of the receiver clock jitter.

• Proceedings of the IEEK Conference
• /
• 1998.06a
• /
• pp.110-113
• /
• 1998

An analysis of the relationship between a linear amplifier chain and an analog-to-digital converter(ADC) in a digital microwave widevand receiver, with respect to sensitivity and dynamic range issues, is presented. The effects of gain, third-order intermodulation products and ADC characteristics on the performance of the receiver are illustrated and design criteria for the linear amplifier chain given a specified ADC are developed. A computer program is used to calculate theretical receiver performance based on gain and third-order intermodulation product selections. Simulated results are also presented and compared with theoretical values.

• Journal of Korea Multimedia Society
• /
• v.15 no.3
• /
• pp.364-371
• /
• 2012

Currently, CMMB(China Mobile Multimedia Broadcasting) and the conventional analog TV broadcasting have transmitted by using UHF(Ultra High Frequency : 474MHz~754MHz) band. Normally, the transmission power of the digital TV broadcasting is lower than the conventional analog TV broadcasting to protect the reception quality of the conventional analog TV broadcasting. The reception sensitivity of CMMB receiver has severely deteriorated due to adjacent the conventional analog TV broadcasting signals which called ACI (Adjacent Channel Interference). To improve the reception sensitivity of a CMMB receiver on ACI environment, this paper proposed a simple method which is tuning a cut off frequency of LPF (Low Pass Filter). From the experiment, the reception sensitivity of CMMB receiver was improved as 11.3dB.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.2
• /
• pp.111-116
• /
• 2003

In this paper, a CMOS baseband analog receiver for wireless home network is discussed. It is composed of a Gilbert type mixer, an Elliptic 6th order 1ow pass filter, and a 6-bit A/D converter. The main role of the mixer is generating a mixed analog signal between the 200MHz output signal of CMOS RF stage and the 199MHz local oscillator. After the undesired high frequency component of the mixed signal comes out. Finally, the analog signal is converted into digital code at the 6-bit A/D converter, The proposed receiver is fabricated with 0.25${\mu}{\textrm}{m}$ 1-poly 5-metal CMOS technology, and the chip area is 200${\mu}{\textrm}{m}$ X1400${\mu}{\textrm}{m}$. the receiver consumes 130㎽ at 2.5V power supply.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.3
• /
• pp.300-311
• /
• 2016

The analog-to-digital-converter-based (ADC-based) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both front-end ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using system-level models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.3
• /
• pp.168-173
• /
• 2004

A low power CMOS receiver baseband analog circuit based on alternating filter and gain stage is reported. For the given specifications of the baseband analog block, optimum allocation of the gain, IIP3 and NF of the each block was performed to minimize current consumption. The fully integrated receiver BBA chain is fabricated in $0.18\;{\mu}m$ CMOS technology and IIP3 of 30 dBm with a gain of 55 dB and noise figure of 31 dB are obtained at 4.86 mW power consumption.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.23 no.5
• /
• pp.109-114
• /
• 2023

In this paper, a 2-channel Image-Reject receiver using a 65-nm CMOS process is presented for Ka-band compact radars. The designed receiver consists of Low-Noise Amplifier (LNA), IQ mixer, and Analog Baseband (ABB). ABB includes a complex filter in order to suppress unwanted images, and the variable gain amplifiers (VGAs) in RF block and ABB have gain tuning range from 4.5-56 dB for wide dynamic range. The gain of the receiver is controlled by on-chip SPI controllers. The receiver has noise figure of <15 dB, OP1dB of >4 dBm, image rejection ratio of >30 dB, and channel isolation of >45 dB at the voltage gain of 36 dB, in the Ka-band target frequency. The receiver consumes 420 mA at 1.2 V supply with die area of 4000×1600 ㎛.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.10
• /
• pp.22-27
• /
• 1996

A digital logic demodulator for binary FSK signals is presented. The operation is based on the quadricorrelator which is known as an ideal frequency detector. The demodulator is especially suitable for high-speed application, and it can be easily implemented in integrated circuit. Computer simulation results show that the performance of the receiver with digital demodulator converges to that of analog quadricorrelator receiver as the number of mixing axes is increased and the optimum bandwidth depending on a modulation index is slightly wider than that of analog demodulator.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.24 no.3
• /
• pp.109-114
• /
• 2024

The effect of inter-channel coupling in multi-channel monopulse receiver is expected to increase by miniaturization trend of receiver. Therefore, in this paper, calibration method is proposed to compensation for inter-channel coupling in receiver of monopulse radar. And it can prevent distortion of angle information of target. Hardware configuration that consists of switch, directional coupler, matched load, ADC(Analog to Digital Converter), signal source of calibration is proposed to calibration. Total nine scattering parameters are obtained by controlling the switch and signal source of calibration. After that, method for restoring the undistorted signal is proposed using the mathematical relationship between the monopulse signal output from the antenna and the monopulse signal passing through the multi-channel receiver in the presence of inter-channel coupling.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.4
• /
• pp.309-317
• /
• 2011

This paper describes a baseband analog (BBA) chain for wireless local area network (WLAN) applications. For the given specifications of the receiver BBA chain, the optimum allocation of the gain and filter rejection of each block in a BBA chain is achieved to maximize the SFDR. The fully integrated BBA chain is fabricated in 0.13 ${\mu}m$ CMOS technology. An input-referred third-order intercept point (IIP3) of 22.9 dBm at a gain of 0.5 dB and an input-referred noise voltage (IRN) of 32.2 nV/${\surd}$Hz at a gain of 63.3 dB are obtained. By optimizing the allocation of the gain and filter rejection using the proposed design methodology, an excellent SFDR performance of 63.9 dB is achieved with a power consumption of 12 mW.