JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Optimization of Low Power CMOS Baseband Analog Filter-Amplifier Chain for Direct Conversion Receiver

  • Published : 2004.09.30
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Abstract

A low power CMOS receiver baseband analog circuit based on alternating filter and gain stage is reported. For the given specifications of the baseband analog block, optimum allocation of the gain, IIP3 and NF of the each block was performed to minimize current consumption. The fully integrated receiver BBA chain is fabricated in $0.18\;{\mu}m$ CMOS technology and IIP3 of 30 dBm with a gain of 55 dB and noise figure of 31 dB are obtained at 4.86 mW power consumption.

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References

  1. P. Choi et aI., 'An experimental coin-sized radio for extremely low power WPAN application at 2.4GHz,' IEEE lSSCC, Feb. 2003, pp. 92-93 https://doi.org/10.1109/ISSCC.2003.1234221
  2. C. Cojocaru et al., 'A 43mW Bluetooth transceiver with -91dBm sensitivity,' IEEE ISSCC, Feb. 2003, pp.90-91 https://doi.org/10.1109/ISSCC.2003.1234220
  3. T. Soorapanth, et al., 'RF Linearity of short-channel MOSFETs,' 1st International Workshop on Design of Mixed-Mode Integrated Circuit and Applications, pp.81-84, 1997
  4. A. A. Abidi, 'General relations between lP2, IP3 and offsets in differential circuit and the effects of feedback' , IEEE Transaction on Microwave Theory and Techniques, vol.51, no.5, pp.1610-1612, May., 2003 https://doi.org/10.1109/TMTT.2003.810147
  5. R. Harjani, J. Kim, and J. Harvey, 'DC coupled IF stage design for a 900-MHz ISM receiver', in IEEE Journal of Solid-State Circuit, vol.38, no.1, pp.126-134, Jan., 2003 https://doi.org/10.1109/JSSC.2002.806259