• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.343-343
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• 2011

저온에서의 Thin Film Transistor (TFT) 혹은 Nonvolatile memory (NVM) 등의 MOS 구조 소자들의 높은 전기적 특성에 관한 연구들이 진행 되면서 mobility와 stability 그리고 구조화의 용이성에 대한 연구가 진행됨에 따라 amorphous silicon의 결정화를 통해 전기적 특성을 향상 시킨 Nanocrystalline silicon (nc-Si)/Microcrystalline silicon (${\mu}c$-Si)에 대한 연구가 관심을 받고 있다. 본 논문에서는 ${\leq}300^{\circ}C$에서 Inductively coupled plasma chemical vapor deposition를 이용한 TFT을 제작하였다. 가스비, 온도, 두께에 따른 결정화 정도를 Raman spectra를 통해 확인한 후 Bottom gate와 Top gate 구조의 TFT를 제작 하고 결정화에 따른 전기적 특성 향상과 그의 덧붙여 플라즈마 처리를 통한 특성 향상을 확인 하였다.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1050-1053
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• 2002

In this paper, Amorphous silicon on glass substrate was recrystallized to poly-crystalline silicon by solid phase crystallization (SPC) technology. The active region of thin film transistor (TFT) was fabricated by amorphous silicon. The output and transfer characteristics of thin film transistor with lightly doped drain (LDD) structure was measured and analyzed. As a results, analyzed TFTs reliability with LDD's length by various kinds argument such as sub-threshold swing coefficient, mobility and threshold voltages were evaluated. Stress effects in TFT were able to improve to the characteristics of turn-on current and hot carrier effects by LDD's length variations.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.453-458
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• 1987

Amorphous silicon thin-film transtors (TFT's) have been designed and fabricated on glass substrates. The hydrogenated amorphous silicon (a-Si:H) thin-film has been deposited by decomposing silane(SiH4) in hydorgen ambient by rf glow discharge method. Amorphous silicon nitride(a-Si:H) has been chosen as the gate dielectric material. It has been prepared by decomposing the mixed gas of silane(SiH4) and ammonia(NH3). The electrical properties and performance characteristics of the thin-film transistrs have been measured and compared with the requirements for the switching elements in liquid crystal flat panel display. The results show that liquid crystal flat panel displays can be fabricated using the thin-film transistors described in this paper.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.10
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• pp.790-795
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• 1998

Fabrication of inverted staggered power TFT devices and electrical characteristic were investigated. 16 fingers with drain and source electrode of TFT and 100V output voltage were designed successfully. It is observed that as $V_g$ increased, $I_d$ increase exponentially. Because of localized deep states of a-Si, $I_d$ shows irregular variation at low voltage. Output and transfer characteristic showed the same as typical variation. But electrical characteristic strongly depend on the channel length and thickness of silicon nitride and amorphous silicon.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.20-28
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• 2003

In this paper, we present results of the comparative analysis of the flicker phenomena in the poly-Si TFT-LCD and a-Si:H TFT-LCD arrays for the development and manufacturing of wide-area and high-quality TFT-LCD displays. We used four different types of TFTs; a-Si:H TFT, excimer laser annealed (ELA) poly-Si TFT, silicide mediated crystallization (SMC) poly-Si TFT, and counter-doped lateral body terminal (LBT), poly-Si TFT. We defined the electrical quantity of the flicker so that we could compare the flickers quantitatively for four different 40" UXGA TFT-LCDs. We identify three factors contributing to the flicker, such as charging time, kickback voltage and leakage current, and analyze how much each of three factors give rise to the flincker in the different TFT-LCD arrays. In addition, we suggest and show that, in the case of the poly-Si TFT-LCD arrays, the low-level (minimum) gate voltages should be carefully chosen to minimize the flicker because of their larger leakage currents compared with a-Si TFT-LCD arrays.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.258-258
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• 2016

최근 디스플레이 산업의 발전에 따라 고성능 디스플레이가 요구되며, 디스플레이의 백플레인 (backplane) TFT (thin film transistor) 구동속도를 증가시키기 위한 연구가 활발히 진행되고 있다. 트랜지스터의 구동속도를 증가시키기 위해 높은 이동도는 중요한 요소 중 하나이다. 그러나, 기존 백플레인 TFT에 주로 사용된 amorphous silicon (a-Si)은 대면적화가 용이하며 가격이 저렴하지만, 이동도가 낮다는 (< $1cm2/V{\cdot}s$) 단점이 있다. 따라서 전기적 특성이 우수한 산화물 반도체가 기존의 a-Si의 대체 물질로써 각광받고 있다. 산화물 반도체는 비정질 상태임에도 불구하고 a-Si에 비해 이동도 (> $10cm2/V{\cdot}s$)가 높고, 가시광 영역에서 투명하며 저온에서 공정이 가능하다는 장점이 있다. 하지만, 차세대 디스플레이 백플레인에서는 더 높은 이동도 (> $30cm2/V{\cdot}s$)를 가지는 TFT가 요구된다. 따라서, 본 연구에서는 차세대 디스플레이에서 요구되는 높은 이동도를 갖는 TFT를 제작하기 위하여, amorphous In-Ga-Zn-O (a-IGZO) 채널하부에 화학적으로 안정하고 전도성이 뛰어난 SnO2 채널을 얇게 형성하여 TFT를 제작하였다. 표준 RCA 세정을 통하여 p-type Si 기판을 세정한 후, 열산화 공정을 거쳐서 두께 100 nm의 SiO2 게이트 절연막을 형성하였다. 본 연구에서 제안된 적층된 채널을 형성하기 위하여 5 nm 두계의 SnO2 층을 RF 스퍼터를 이용하여 증착하였으며, 순차적으로 a-IGZO 층을 65 nm의 두께로 증착하였다. 그 후, 소스/드레인 영역은 e-beam evaporator를 이용하여 Ti와 Al을 각각 5 nm와 120 nm의 두께로 증착하였다. 후속 열처리는 퍼니스로 N2 분위기에서 $600^{\circ}C$의 온도로 30 분 동안 실시하였다. 제작된 소자에 대하여 TFT의 전달 및 출력 특성을 비교한 결과, SnO2 층을 형성한 TFT에서 더 뛰어난 전달 및 출력 특성을 나타내었으며 이동도는 $8.7cm2/V{\cdot}s$에서 $70cm2/V{\cdot}s$로 크게 향상되는 것을 확인하였다. 결과적으로, 채널층 하부에 SnO2 층을 형성하는 방법은 추후 높은 이동도를 요구하는 디스플레이 백플레인 TFT 제작에 적용이 가능할 것으로 기대된다.

• Journal of the Korean institute of surface engineering
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• v.43 no.1
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• pp.7-11
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• 2010

Solid phase crystallization (SPC) is a simple method in producing a polycrystalline phase by annealing amorphous silicon (a-Si) in a furnace environment. Main motivation of the crystallization technique is to fabricate low temperature polycrystalline silicon thin film transistors (LTPS-TFTs) on a thermally susceptible glass substrate. Studies on SPC have been naturally focused to the low temperature regime. Recently, fabrication of polycrystalline silicon (poly-Si) TFT circuits from a high temperature polycrystalline silicon process on steel foil substrates was reported. Solid phase crystallization of a-Si films proceeds by nucleation and growth. After nucleation polycrystalline phase is propagated via twin mediated growth mechanism. Elliptically shaped grains, therefore, contain intra-granular defects such as micro-twins. Both the intra-granular and the inter-granular defects reflect the crystallinity of SPC poly-Si. Crystallinity and SPC kinetics of high temperatures were compared to those of low temperatures using Raman analysis newly proposed in this study.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.5
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• pp.531-539
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• 1991

We develop an analytical model of the static and the dynamic characteristics of amorphous silicon thin film transistors (a-Si TFTs) in order to incorporate into a widely used circuit simulator such as SPICE. The critical parameters considered in our analytical model of a-Si TFT are the power factor (XN) of saturation source-drain current and the effective channel length (L') at saturation region. The power factor, XN must not always obey so-called

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.57-62
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• 1999

Polycrystaline thin film transistors are fabricated on the transparent glass substrate by a lamp-scan annealing. The line-shaped lamp scanning method, which is profitable for large area process, effectively radiated silicon film on glass substrate. Amorphous silion film absorbs the light which is emitted from halogen-lamp and it transformed into crystalline silicon by metal-induced lateral crystallization. In order to enhance the annealing effect, capping layer was deposited on the whole substrate. When the scan speed was 1-2mm/sec, lateral crystallization of amorphous silicon under capping layer was 18~27${\mu}m/scan$. The thin film transistor fabricated by this method shows high electron mobility over 130$cm^2/V{\cdot}sec$

• The Transactions of the Korean Institute of Electrical Engineers
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• v.41 no.2
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• pp.163-169
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• 1992

A new analytical expression for the temperature variation characteristics of hydrogenerated amorphous silicon thin film transistors(a-si:H TFT), between 223K and 433K, is presented and experimentally verified. The results show that the experimental transfer and output characteristics at several temperatures are easily modeled between -5$0^{\circ}C$ and 9$0^{\circ}C$. The model is based on three functions obtained from the experimental data of IS1DT versus VS1GT. Theoretical results confirm the simple form of the model in terms of the device geometry. It was determined that as the temperature increased, the saturated drain current increased and, at a fixed gate voltage, the device saturated at increasingly larger drain voltages while the threshold voltages decreased.