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Power-based Side-Channel Analysis Against AES Implementations: Evaluation and Comparison

  • Benhadjyoussef, Noura;Karmani, Mouna;Machhout, Mohsen
    • International Journal of Computer Science & Network Security
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    • v.21 no.4
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    • pp.264-271
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    • 2021
  • From an information security perspective, protecting sensitive data requires utilizing algorithms which resist theoretical attacks. However, treating an algorithm in a purely mathematical fashion or in other words abstracting away from its physical (hardware or software) implementation opens the door to various real-world security threats. In the modern age of electronics, cryptanalysis attempts to reveal secret information based on cryptosystem physical properties, rather than exploiting the theoretical weaknesses in the implemented cryptographic algorithm. The correlation power attack (CPA) is a Side-Channel Analysis attack used to reveal sensitive information based on the power leakages of a device. In this paper, we present a power Hacking technique to demonstrate how a power analysis can be exploited to reveal the secret information in AES crypto-core. In the proposed case study, we explain the main techniques that can break the security of the considered crypto-core by using CPA attack. Using two cryptographic devices, FPGA and 8051 microcontrollers, the experimental attack procedure shows that the AES hardware implementation has better resistance against power attack compared to the software one. On the other hand, we remark that the efficiency of CPA attack depends statistically on the implementation and the power model used for the power prediction.

Clinical Characteristics and Treatment of Immune-Related Adverse Events of Immune Checkpoint Inhibitors

  • Juwhan Choi;Sung Yong Lee
    • IMMUNE NETWORK
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    • v.20 no.1
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    • pp.9.1-9.21
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    • 2020
  • Immune checkpoint inhibitors (ICIs) have been changing the paradigm of cancer treatment. However, immune-related adverse effects (irAEs) have also increased with the exponential increase in the use of ICIs. ICIs can break up the immunologic homeostasis and reduce T-cell tolerance. Therefore, inhibition of immune checkpoint can lead to the activation of autoreactive T-cells, resulting in various irAEs similar to autoimmune diseases. Gastrointestinal toxicity, endocrine toxicity, and dermatologic toxicity are common side effects. Neurotoxicity, cardiotoxicity, and pulmonary toxicity are relatively rare but can be fatal. ICI-related gastrointestinal toxicity, dermatologic toxicity, and hypophysitis are more common with anti- CTLA-4 agents. ICI-related pulmonary toxicity, thyroid dysfunction, and myasthenia gravis are more common with PD-1/PD-L1 inhibitors. Treatment with systemic steroids is the principal strategy against irAEs. The use of immune-modulatory agents should be considered in case of no response to the steroid therapy. Treatment under the supervision of multidisciplinary specialists is also essential, because the symptoms and treatments of irAEs could involve many organs. Thus, this review focuses on the mechanism, clinical presentation, incidence, and treatment of various irAEs.

Formal Verification of AES Encryption Module Using CBMC (CBMC를 이용한 AES 암호화 모듈의 정형 검증)

  • Ahn Young-Jung;Choi Jin-Young
    • Proceedings of the Korean Information Science Society Conference
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    • 2005.11a
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    • pp.97-99
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    • 2005
  • 정보보호 제품의 주요한 역할을 담당하는 암호 모듈의 구현 무결성을 보증하기 위해 많은 연구가 활발히 이루어지고 있다. 하지만 기존의 일반적인 테스팅 방법으로는 구현 무결성에 대해 신뢰하지 못한다. 본 논문에서는 NIST (the US National Institute of Science and Technology)에서 AES(Advanced Encryption Standard)로 제정된 Rijndael 블록암호 모듈을 Verilog로 구현하고 CBMC를 이용하여 새로운 방식의 구현 무결성 평가 방법을 제시하고자 한다.

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VHDL Design of AES-128 Crypto-Chip (AES-128 암호화 칩의 VHDL 설계)

  • 김방현;김태큐;김종현
    • Proceedings of the Korean Information Science Society Conference
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    • 2002.04a
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    • pp.862-864
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    • 2002
  • 정보 보안을 위한 암호화 처리는 각종 컴퓨터 시스템이나 통신시스템에서 부가적으로 수행되기 때문에암호화 속도가 느린 경우에는 시스템의 속도 지연을 유발시키게 된다. 따라서 고속의 컴퓨터 연산이나 고속통신에 있어서 이에 맞는 고속의 암호화는 필수적으로 해결되어야 할 과제인데, 이것은 암호화 및 복호화를 하드웨어로 처리함으로서 가능하다. 본 연구에서는 차세대 표준 암호화 알고리즘인 AES-128의 암호화와 복호화를 단일 ASIC칩에 구현하고, 인터페이스 핀의 수와 내부 모듈간의 버스 폭에 따른 칩의 효율성을 평가하였다. 이 연구에서 VHDL 설계 및 시뮬레이션은 Altera 사의 MaxPlus 29.64를 이용하였으며, ASIC 칩은 Altera 사의 FLEXIOK 계열의 칩을 사용하였다.

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The discharge characteristics and ICP-AES analysis of insulators by surface deterioration (애자 표면열화에 의한 방전특성과 ICP-AES 분석)

  • Shong, Kil-Mok;Kim, Young-Seok;Jung, Jin-Soo
    • Proceedings of the KIEE Conference
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    • 2009.07a
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    • pp.1408_1409
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    • 2009
  • It's described the discharge characteristics and ICP-AES analysis of insulators by surface deterioration in this paper. For the assessment of insulators, there are applied the conductivity of dusts, contact angle measurement of the insulator surfaces and the ingredient analysis in each area. Through the analysis of pollutants attached to insulators inside the tunnel, the cleaning cycle is discussed. As the results, it would be expected to the electrical safety.

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AES Modules for IPSec Hardware Chips in IPv6 (IPv6용 IPSec 하드웨어 칩을 위한 AES 모듈)

  • 김경태;김지욱;박상길;양인제;김동규;이정태
    • Proceedings of the Korea Multimedia Society Conference
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    • 2002.05d
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    • pp.920-925
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    • 2002
  • 급속히 고갈되어가는 IPv4의 주소 부족 문제를 해결하기 위하여, 차세대 인터넷 프로토콜 (IP)인 IPv6가 제안되었고 실용화 단계까지 진행되고 있다. IPv6에서의 요구 사항 중의 하나인 IPSec은 IPv4의 취약한 보안 기능을 강화하는 것이다. 현재 IPSec에서 반드시 구현되어야 할 암호화 알고리즘으로 MD5, SHA1, 3DES와 더불어 최근 표준안으로 채택된 AES(Rijndael)을 요구하고 있다. IPv6의 고속 수행을 위하여는 IPSec이 하드웨어로 구현될 필요성이 있으므로, 본 논문에서는 IPv6용 IPSec 칩에 탑재할 AES 하드웨어 모듈을 구현하였다. 제안된 하드웨어 모듈은 효율적인 알고리즘의 수행과 구현을 위하여, 암호화/복호화 단계가 동일한 구조로 동작하도록 설계하였으며, 가변적인 128, 196,256 비트의 키에 대하여 같은 로직을 사용하도록 설계하였다.

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Design of Cryptographic Processor for AES Rijndael Algorithm (AES Rijndael 알고리즘용 암호 프로세서의 설계)

  • 최병윤
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.10B
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    • pp.1491-1500
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    • 2001
  • 본 논문에서는 AES Rijndael 암호 알고리즘을 구현하는 암호 프로세서를 설계하였다. 하드웨어 공유를 통해 면적을 감소시키기 위해 1라운드 동작을 2개의 부분 라운드로 나누고 각 부분 라운드를 4 클록으로 구현하였다. 라운드 당 평균 5 클록의 연산 효율을 만들기 위해 인접한 라운드간에 부분 라운드 라이프라인 동작 기법을 적용하고, 키 설정 오버헤드 시간을 배제하기 위해, 암호 및 복호 동작의 라운드 키를 온라인 계산 기법을 사용하여 생성하였다. 그리고 다양한 응용 분야에 적용하기 위해, 128, 192, 256 비트의 3가지 암호 키를 모두 지원할 수 있도록 하였다. 설계된 암호 프로세서는 약 36,000개의 게이트로 구성되며 0.25$\mu\textrm{m}$ CMOS 공정에서 약 200Mhz의 동작 주파수를 가지며, 키 길이가 128 비트인 AES-128 ECB 동작 모드에서 약 512 Mbps의 암.복호 율의 성능을 얻을 수 있었다.

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TEM/AES Analysis of AlGaAs/gaAs Quantum Well Structures Grown by LP-MOCVD (저압MOCVD법에 의하여 성장한 AlGaAs/GaAs. 양자우물구조의 TEM/AES분석)

  • 김광일;정욱진;배영호;김재남;정동호;정윤하
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.5
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    • pp.716-723
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    • 1990
  • Transmission electron microscopy (TEM) and anger electron microscopy(AES) studies of GaAs/AlxGa1-xAs(x=0.58) quantum wells grown by low pressure metalorganic chemical vapor deposition(LP-MOCVD) are carried out. Isolated quantum well structure having the well width as small as 15 \ulcornerand multiquantum well structure, which consisted of 51 alternating layers with each thickness of 10\ulcorner were suscessfully grown. TEM analyses have shown that their interfaces were almost completely coherent without any structural disorder, alloy clustering and crystal defect. AES depth resolution have shown the compositional periodicity of superlattice structure.

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Removal of OH Spectral Interferences from Aqueous Solvents in Inductively Coupled Plasma-Atomic Emission Spectrometry (ICP-AES) with Ar Cryogenic Desolvation

  • Cho, Young-Min;Pak, Yong-Nam
    • Bulletin of the Korean Chemical Society
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    • v.26 no.9
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    • pp.1415-1420
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    • 2005
  • The spectral interferences of OH from aqueous solvents in ICP-AES have been studied and eliminated using a cryogenic argon trap. The prominent lines of Bi I 306.772 nm, Al I 309.271 nm, and V II 310.230 nm, which are very seriously overlapped with the OH band, were examined. With an extended torch and high tangential flow of 20 L/min, water vapor from air entrainment was prevented. The combination of a condenser and argon cryogenic trap was able to eliminated most of water vapor carried by the argon sample gas. Removal of OH spectral interference could extend the linearity of the calibration curve 5-10 times on the lower concentration for ICP-AES. Interference Equivalent Concentration (IEC) has been reduced to 5.6, 5.9, and 12.4 times for Bi, Al and V, respectively.

The Chemical COmposition Analysis by AES and XPS of PbTiO$_3$ Thin Films Fabricated by CVD (화학증착법에 의해 제조된 PbTiO$_3$ 박막의 AES와 XPS에 의한 조성분석)

  • Soon Gil Yoon;Ho Gi Kim
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1989.06a
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    • pp.83-86
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    • 1989
  • Lead titanate thin films with a perovskite structure were successfully structure were successfully fabricated on titanium substrate by Chemical Vapour Deposition(CVD). Analyses of Auger Electron Spectroscopy(AES) and X-ray Photoelectron Spectroscopy (XPS) have been performed in order to find a chemical composition of lead titanate films. The analysis of chemical composition by AES and XPS was investigated for variations of deposition temperature and Ti(C$_2$H$_{5}$O)$_4$ fractions. The chemical composition of PbTiO$_3$by XPS analysis was almost constant regardless of deposition parameters and the comparison of chemical composition by AES and XPS was performed.d.

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