• 전자공학회논문지D
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• 제35D권3호
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• pp.46-55
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• 1998

This stud demonstrates the profiles of heavy ions (As, Sb) in silicon by high energy (1~10 MeV) implantation. Implanted profiles were measured by SIMS (Cameca 4f) and compared with simulation results (TRIM) program and analytical description method using Pearson function). The experimental results have a little bit deviation with simulation data in the case of As high energy implatation. But in the case of Sb, the experimental results are in good agreement with TRIM data. SIMS profiles are perfectly fitted with a analytical description method only using one pearson function in Sb implantation. but in the case of As, fitted profilesshow with a little bit deviations by channeling effects of SIMS profiles. Thermal annealing for electrical activation of implanted ions was carried out by furnace annealing and RTA(Rapid Thermal Annealing). Concentration-depth profile after heat treatement were measured by SR(Spreading Resistance) method.

• 전자공학회논문지A
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• 제30A권8호
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• pp.42-48
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• 1993

Ar ions were implanted at 1 MeV into (100)Cz Si wafers with dose of 1 * 10$^{15}$ ions/cm$^{2}$. Damage induced by high energy implantation and its annealing behavior during rapid thermal annealing for 10sec at temperatures from 550 to 1100${\circ}C$ were investigated by crosssection transmission electron microscopy study. It can be clearly seen from the observation that the SPE(Solid Phase Epitaxy) regrowth of the buried amorphous layer induced by ion implantation proceeds from both upper and lower amorphous/crystalline (a/c) interfaces, and the activation energy for SPE from interfaces were both 1.43eV. Misfit dislocation where two interfaces met was formed and it coalesced into the hair pin dislocation in the upper regrown region. At the higher temperature after annealing out of the misfit dislocation, hair pin dislocations showed considerable drop in its bandwidth. However, they were not disappeared even at the temperature 1100${\circ}C$ with the end of range dislocation loops which were formed at the original lower a/c interface.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.354-357
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• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.115-117
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• 2005

In this paper, we formed the shallow junction by preamorphization and low energy ion implantation. And a simulator is designed for predicting the annealing process results. Especially, if considered the applicable to single step annealing process(RTA, FA) and dual step annealing process(RTA+FA, FA+RTA). In this simulation, the ion implantation model and the boron diffusion model are used. The Monte Carlo model is used for the ion implantation. Boron diffusion model is based on pair diffusion at nonequilibrium condition. And we considered that the BI-pairs lead the diffusion and the boron activation and clustering reaction. Using the boundary condition and initial condition, the diffusion equation is solved successfully. The simulator is made ofC language and reappear the experimental data successfully.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 춘계학술대회 논문집 디스플레이 광소자 분야
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• pp.127-130
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• 2005

The properties of phosphorus doped ZnO multilayer thin films deposited on (001) sapphire substrates by pulsed laser deposition (PLD) were investigated by using annealing treatment at various annealing temperature after deposition. The phosphorus doped ZnO multilayer was composed of phosphorus doped ZnO layer and two pure ZnO layers on sapphire substrate. The structural. electrical and optical properties of the ZnOthin films were measured by X-ray diffraction (XRD). Hall measurements and photoluminescence (PL). As the annealing temperature optimized. the electrical properties of the ZnO multilayer showed a electron concentration of $1.56{\times}10^{16}/cm^3$, a resistivity of 17.97 ${\Omega}cm$. It was observed the electrical property of the film was changed by dopant activation effect as thermal annealing process

• 전자공학회논문지A
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• 제28A권12호
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• pp.59-64
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• 1991

Thin (25-103$\AA$) SiO$_2$ films are grown using the rapid thermal oxidation processing at temperatures of 105$0^{\circ}C$-115$0^{\circ}C$ for 5-30 sec, in order to investigate the characteristics of ultra thin oxide. For measuring the thickness of oxide TEM, ellipsometry, and C-V method which is taken in the condition of small surface band bending are used and compared. When neglecting the small deviation affected by both interface state and moisture charge effect, those three methods described above give similar results. In order to examine the effect of rapid thermal annealing, part of samples are annealed in N$_2$ ambient. MOS capacitors are fabricated and the characteristics of I-V and C-V are measured. Measurements show that the activation energy of initial thickness of oxide grown during the ramp-up time is of 1.125eV and the activation energy of the oxidation rate is of 0.98eV. As oxidation temperature is increased, dielectric breakdown field E$_{BD}$ is decreased due to the increase of fixed charge density N$_f$ However, E$_{BD}$ is shown to be decreased as increasing the thickness of oxide. The increase of N$_f$ in the early stage of thermal annealing results in the decrease of E$_{BD}$.

• 열처리공학회지
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• 제12권4호
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• pp.287-293
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• 1999

Effect of heat-treatment on the microstructure and recrystallization behavior of pure Zr was studied. The specimens were prepared under the various annealing temperatures from $400^{\circ}C$ to $800^{\circ}C$ and times from 300 to 5000 minutes after vacuum arc remelting. The recrystallization behavior was observed by a polarized optical microscope, TEM and micro-vickers hardness tester. With increasing the annealing time, the temperature region of hardness drop moved to the lower temperature region due to the recovery and recrystallization behaviors at the lower temperature. The recrystallization of cold-worked pure Zr was completed between 450 and $600^{\circ}C$. The size of recrystallized grain increased at $700^{\circ}C$ for 600min. Activation energy(Q) of pure Zr measured by the time for constant fraction technique was 78 KJ/mol.

• 한국표면공학회지
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• 제29권5호
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• pp.325-329
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• 1996

We report on p-type arsenic doping of metalorganic vapor phase epitaxially (MOVPE) grown HgCdTe on (100) GaAs. HgCdTe was grown at $370^{\circ}C$ in a horizontal reactor with using dimethy-cadmium, diisoprophyltelluride, and elemental Hg. We used tris-dimethylaminoarsenic (DMAAs) as the metalorganic for p-doping. 4micron thick CdTe and subsequently 10micron thick HgCdTe were grown on (100) GaAs substrate. Interdiffused multilayer process in which thin CdTe and HgTe layers are grown alternately and interdiffused to obtain homogeneous HgCdTe alloys was used. Arsenic was doped during CdTe growth cycle. After growth HgCdTe was annealed at $415^{\circ}C$ for 15 min and then annealed again at $220^{\circ}C$ for 3 hr, both with Hg-saturate condition. We could obtain p-doping from 2.5$\times$$10^{16}$ to 6.6$\times$$10^{17}$$cm^{-3}$, depending on the DMAAs partial pressure. With the dual Hg-annealing, activation of arsenic was aboutt 90%, which was confirmed by SIMS measurement. With only low temperature annealing at $220^{\circ}C$ for 3hr, activation efficiency was about 50%.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1995년도 추계학술대회 논문집
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• pp.89-93
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• 1995

Effects of hydrogenation in amorphous silicon rile growths on Solid Phase Crystallization (SPC) was investigated using x-ray diffractometry, energy dispersive Spectroscopy, and Raman spectrum. Interdiffusion of barium(Ba) and aluminum(Al) compounds of corning substrate was observed in both of rf sputtering and LFCVD films under the low temperature(580$^{\circ}C$) annealing. Low degree of crystallinity resulted from the interdiffusion was obtained. Highly applicable degree of crystallinity was obtained through the mechanical damage induced surface activation on amorphous silicon films. X-ray diffraction intensity of (111) orientation was used to characterize the degree of crystallinity of SPC. Nucleation and growth rate in SPC could be controllable through the employed surface treatment. IIydrogenated LPCVD films showed the superior crystallinity to non-hydrogenated sputtering films. Insignificant effects of activation treatment in sputtered film was of activation treatment in sputtered film was observed on SPC.

• 열처리공학회지
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• 제23권5호
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• pp.239-244
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• 2010

Influence of Zr addition on grain stability at elevated temperatures has been investigated for extruded pure Mg and Mg-0.25%Zr alloy. The grain size of pure Mg increases rapidly with increasing annealing temperature when isochronally annealed for 60 min from 573 to 773 K, whereas the grains are stable up to 723 K for the Zr-containing alloy. The activation energies for grain growth ($E_g$) at this temperature range were determined as 75.3 and 105.9 kJ/mole for the pure Mg and Mg-0.25%Zr alloy, respectively. TEM observations on the annealed Mg-Zr samples revealed that higher thermal stability and higher activation energy for grain growth resulting from Zr addition in Mg may well be associated with the restriction of grain growth by nano-sized Zr particles distributed in the microstructure.