• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.453-458
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• 1987

Amorphous silicon thin-film transtors (TFT's) have been designed and fabricated on glass substrates. The hydrogenated amorphous silicon (a-Si:H) thin-film has been deposited by decomposing silane(SiH4) in hydorgen ambient by rf glow discharge method. Amorphous silicon nitride(a-Si:H) has been chosen as the gate dielectric material. It has been prepared by decomposing the mixed gas of silane(SiH4) and ammonia(NH3). The electrical properties and performance characteristics of the thin-film transistrs have been measured and compared with the requirements for the switching elements in liquid crystal flat panel display. The results show that liquid crystal flat panel displays can be fabricated using the thin-film transistors described in this paper.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.821-825
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• 2004

The a-Si：H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si：H TFTs is inverted staggered. The gate electrode is formed by patterning with length of 8 ${\mu}m∼16 ${\mu}m. and width of 80∼200 ${\mu}m after depositing with gate electrode (Cr) 1500 under coming 7059 glass substrate. We have fabricated a-SiN：H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN：H (2000 ), a-Si：H(2000 ) and n+a-Si：H (500). We have deposited n+a-Si：H ,NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si：H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si：H TFTs decreasing parasitic capacitance of source-drain has channel length of 8 ~20 ${\mu}m and channel width of 80∼200 ${\mu}m. And it shows drain current of 8 ${\mu}A at 20 gate voltages, Ion/Ioff ratio of 108 and Vth of 4 volts.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.340.2-340.2
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• 2014

최근 비정질 산화물 반도체는 가시광 영역에서의 투명도와 낮은 공정 온도, 그리고 높은 Field-effect mobility로 인해 Thin film transistors의 Active channel layer의 재료로 각광 받고 있다. ZnO, IZO, IGO, ITGO등의 많은 산화물 반도체들이 TFT의 채널층으로의 적용을 위해 활발히 연구되고 있으며, 특히 비정질 IGZO는 비정질임에도 불구하고 Mobility가 $10cm^2/Vs$ 정도로 기존의 a-Si:H 보다 높은 Mobility 특성을 나타내고 있어 대화면 디스플레이와 고속 구동을 위한 LCD에 적용 할 수 있으며 또한 낮은 공정 온도로 인해 플렉서블 디스플레이에 응용될 수 있다는 장점이 있다. 우리는 RF magnetron sputtering법으로 증착한 비정질 IGZO TFT(Thin Film Transistors)의 전기적 특성과 IGZO 박막의 특성에 미치는 RF power의 영향을 연구하였다. 제작한 TFTs의 Active channel layer는 산소분압 1%, Room temperature에서 RF power별(50~150 W)로 Si wafer 기판 위에 30nm로 증착 하였고 100 nm의 $SiO_2$가 절연체로 사용되었다. 또한 박막 특성을 분석하기 위해 같은 Chamber 분위기에서 100 nm로 IGZO 박막을 증착하였다. 비정질 IGZO 박막의 X-ray reflectivity(XRR)을 분석한 결과 RF Power가 50 W에서 150 W로 증가 할수록 박막의 Roughness는 22.7 (${\AA}$)에서 6.5 (${\AA}$)로 감소하고 Density는 5.9 ($g/cm^3$)에서 6.1 ($g/cm^3$)까지 증가하는 경향을 보였다. 또한 제작한 IGZO TFTs는 증착 RF Power가 증가함에 따라 Threshold voltage (VTH)가 0.3~4(V)로 증가하는 경향을 나타내고 Filed-effect mobility도 6.2~19 ($cm^2/Vs$)까지 증가하는 경향을 보인다. 또한 on/off ratio는 모두 > $10^6$의 값을 나타내며 subthreshold slope (SS)는 0.3~0.8 (V/decade)의 값을 나타낸다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.114-121
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• 2001

A circuit model for active-controlled field emitter array(ACFEA) as an electron source of active-controlled field emission display(ACFED) has been proposed. The ACFEA with hydrogenated amorphous silicon thin-film transistor(a-Si:H TFT) and Spindt-type molibdenum tips (Spindt-Mo FEA) has been fabricated monolithically on the same glass. A-Si:H TFT is used as a control device of field emitters, resulting in stabilizing emission current and lowering driving voltage. The basic model parameters extracted from the electrical characteristics of the fabricated a-Si:H TFT and Spindt-Mo FEA were implemented into the ACFEA model with a circuit simulator SPICE. The accuracy of the equivalent circuit model was verified by comparing the simulated results with the measured one through DC analysis of the ACFEA. The transient analysis of the ACFEA showed that the gate capacitance of FEA along with the drivability of TFT strongly affected the response time. With the fabricated ACFEA, we obtained a response time of 15$mutextrm{s}$, which was enough to make 4bit/color gray scale with the pulse width modulation (PWM).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.11a
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• pp.118-121
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• 1995

Fabrication and a new analytical expression for the capacitance characteristics of hydrogenerated amorphous silicon thin film transistors(a-Si:H TFTs) is presented and experimentally verified. The results show that the experimental capacitance characteristics are easily measeured. Measured transfer and DC output characteristic curves of a-Si:H TFT are similar to those of the standard MOSFET-IC. The capacitances on bias voltages are in good agreement with experimental data. This capacitance characteristics is suitable for incorporation into a circuit simulator and can be used for computer-aided design of a-Si thin film transistor integrated circuits.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.711-714
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• 2006

Properties of silicon nitride ($SiN_x$) film including physical and electrical characteristics have been studied for improving the stability of hydrogenated amorphous silicon thin-film transistors (a-Si TFTs) in active-matrix liquid-crystal displays (AMLCDs). The instability of a-Si:H TFTs is estimated by accelerated stress test of both bias-temperature stress and bias-illumination stress. The results show that the deposition conditions of $SiN_x$ films with higher power and lower pressure are the best choice for improving the on-current and stability of TFTs.

• Korean Journal of Materials Research
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• v.17 no.9
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• pp.484-488
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• 2007

Mo(Ti) alloy and pure Cu thin films were subsequently deposited on $SiO_2-coated$ Si wafers, resulting in $Cu/Mo(Ti)/SiO_2$ structures. The multi-structures have been annealed in vacuum at $100-600^{\circ}C$ for 30 min to investigate the outdiffusion of Ti to Cu surface. Annealing at high temperature allowed the outdiffusion of Ti from the Mo(Ti) alloy underlayer to the Cu surface and then forming $TiO_2$ on the surface, which protected the Cu surface against $SiH_4＋NH_3$ plasma during the deposition of $Si_3N_4$ on Cu. The formation of $TiO_2$ layer on the Cu surface was a strong function of annealing temperature and Ti concentration in Mo(Ti) underlayer. Significant outdiffusion of Ti started to occur at $400^{\circ}C$ when the Ti concentration in Mo(Ti) alloy was higher than 60 at.%. This resulted in the formation of $TiO_2/Cu/Mo(Ti)\;alloy/SiO_2$ structures. We have employed the as-deposited Cu/Mo(Ti) alloy and the $500^{\circ}C-annealed$ Cu/Mo(Ti) alloy as gate electrodes to fabricate TFT devices, and then measured the electrical characteristics. The $500^{\circ}C$ annealed Cu/Mo($Ti{\geq}60at.%$) gate electrode TFT showed the excellent electrical characteristics ($mobility\;=\;0.488\;-\;0.505\;cm^2/Vs$, on/off $ratio\;=\;2{\times}10^5-1.85{\times}10^6$, subthreshold = 0.733.1.13 V/decade), indicating that the use of Ti-rich($Ti{\geq}60at.%$) alloy underlayer effectively passivated the Cu surface as a result of the formation of $TiO_2$ on the Cu grain boundaries.

• Journal of the Korean Vacuum Society
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• v.12 no.2
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• pp.130-135
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• 2003

Polycrystalline silicon thin films have been used for low cost thin film device application. However, it was very difficult to fabricate high performance poly-Si at a temperature lower than $600^{\circ}C$ for glass substrate because the crystallization process technologies like conventional solid phase crystallization (SPC) require the number of high temperature (600-$1000^{\circ}C$) process. The objective of this paper is to grow poly-Si on flexible substrate using a rapid thermal crystallization (RTC) of amorphous silicon (a-Si) layer and make the high temperature process possible on molybdenum substrate. For the high temperature poly-Si growth, we deposited the a-Si film on the molybdenum sheet having a thickness of 150 $\mu\textrm{m}$ as flexible and low cost substrate. For crystallization, the heat treatment was performed in a RTA system. The experimental results show the grain size larger than 0.5 $\mu\textrm{m}$ and conductivity of $10^{-5}$ S/cm. The a-Si was crystallized at $1050^{\circ}C$ within 3min and improved crystal volume fraction of 92 % by RTA. We have successfully achieved a field effect mobility over 67 $\textrm{cm}^2$/Vs.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.341.1-341.1
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• 2014

In the advanced material for the next generation display device, transparent amorphous oxide semiconductors (TAOS) are promising materials as a channel layer in thin film transistor (TFT). The TAOS have many advantages for large-area application compared with hydrogenated amorphous silicon TFT (a-Si:H) and organic semiconductor TFT. For the reasonable characteristics of TAOS, The a-IGZO has the excellent performances such as low temperature fabrication (R.T~), high mobility, visible region transparent, and reasonable on-off ratio. In this study, we investigated how the electric characteristics and physical properties are changed as various oxygen ratio when magnetron sputtering. we analysis a-IGZO film by AFM, EDS and I-V measurement. decreasing the oxygen ratio, the threshold voltage is shifted negatively and mobility is increasing. Through this correlation, we confirm the effect of oxygen ratio. We fabricated the bottom-gate a-IGZO TFTs. The gate insulator, SiO2 film was grown on heavily doped silicon wafer by thermal oxidation method. a-IGZO channel layer was deposited by RF magnetron sputtering. and the annealing condition is $350^{\circ}C$. Electrode were patterned Al deposition through a shadow mask(160/1000 um).

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.64-64
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• 1999

다결정 실리콘-게르마늄(poly-SiGe)은 태양전지 및 TFT-LCD와 같은 소자 응용에 있어서 중요하게 연구되고 있는 물질이다. 우리는 수소화된 비정질 실리콘-게르마늄 (a-Si1-xGex:H) 박막을 증착시키고 고상결정화시키며 XRD(x-ray diffraction) 및 ESR (electron spin resonance) 측정을 수행하였다. PECVD 증착가스는 SiH4과 GeH4가스를 사용하였고 Ge의 성분비는 x=0.0, 0.1, 0.5 정도로 조절되었다. 기판은 Corning 1737 glass를 사용하였고, 기판 온도는 20$0^{\circ}C$ 이었다. 증착압력과 r.f. 전력은 각각 0.6Torr와 3W이었다. 증착된 SiGe 박막은 고상결정화를 위해 $600^{\circ}C$ N2 분위기에서 가열되고, 그에 따른 XRD 및 ESR spectrum의 변화를 관찰하였다. ESR 측정은 X-band 그리고 상온에서 행해졌다. 먼저 XRD 측정으로부터 박막의 고상결정화 정도를 알 수 있었고, 고상결정화 과정이 초기 핵형성 단계와 결정화 단계, 그리고 더 이상 결정화가 일어나지 않는 완료 단계로 구분될 수 있음을 보여주었다. X값이 증가함에 따라 결정화 시간은 훨씬 단축되었다. ESR로 측정된 스핀 밀도는 a-Si1-xGex:H 박막이 처음 가열됨에 따라 전체적으로 크게 증가했다가, 결정화가 일어나면서 다시 감소하여 나중에는 거의 변화가 없었다. ESR 신호의 초기 증가는 수소 이탈에 의한 dangling bond의 증가에 기인하며, 다음 단계의 감소 및 안정 상태는 결정화에 따른 결정경계 영역의 감소와 결함들의 안정성에 기인하는 것으로 생각된다. 그러나 흥미로운 것은 Si1-xGex 합금의 경우 가열시간이 증가됨에 따라 Si-db(Si-dangling bond)와 Ge-db에 의한 신호가 서로 분리되어 나타났으며, 이 Si-db 스핀 밀도와 Ge-db 스핀밀도의 변화정도는 x값에 크게 의존함을 보여준 것이다. 즉 순수한 a-Si:H의 경우 Si-db 의 스핀밀도의 증가시간은 4시간 정도였고, 그리고 다시 감소하였으며, x=0.1 인 박막에서 Si-db와 Ge-db의 변화 시간은 순수 S-db 변화의 경우와 거의 유사하였다. 그러나 x=0.5 샘플에서는 Si-db의 변화가 빨라져서 0.1 시간 안에 증가되었고, Ge-db의 변화는 더 빠르게 수 분 동안에 증가 된후 다시 감소하였다. 이것은 수소의 Si에 대한 친화력 뿐 만아니라 Si-H과 Ge-H 결합에너지가 주위 원자들의 구성에 크게 영향받을 수 있는 가능성을 제시해준다.