• 한국전기전자재료학회논문지
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• 제19권11호
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• pp.1044-1049
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• 2006

We reported on characteristics of the fluorescent OLED fabricated on commercial ITO/glass and BCS grown IZO/glass substrate, respectively. The amorphous IZO anode film grown by box cathode sputtering(BCS) exhibited similar electrical and optical characteristics to commercial ITO anode even though it was deposited at room temperature. In addition, the amorphous IZO anode showed higher workfunction (5.2 eV) than that of the commercial ITO anode (5.0 eV) after ozone treatment for 10 min. Furthermore, fluorescent OLED fabricated on amorphous IZO anode film showed improved current-voltage-luminance characteristics, external quantum efficiency and power efficiency en contrast with fluorescent OLED fabricated on commercial ITO anode film. It was thought that smooth surface and high workfunction of amorphous IZO anode lead to more efficient hole injection by reduction of interface barrier height between anode and organic layers.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.147-152
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• 2016

In this study, we fabricated Ag-based electrochemical metallization memory devices which is also called conductive-bridge random-access memory (CBRAM) in order to investigate the resistive switching behavior depending on the bottom electrode (BE). RRAM cells of two different layer configurations having $Ag/Si_3N_4/TiN$ and $Ag/Si_3N_4/p^+$ Si are studied for metal-insulator-metal (MIM) and metal-insulator-silicon (MIS) structures, respectively. Switching voltages including forming/set/reset are lower for MIM than for MIS structure. It is found that the workfunction different affects the performances.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.97-98
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• 2009

Tunneling barrier engineered charge trap flash (TBE-CTF) memory capacitor were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectrics layers were used as engineered tunneling barrier. The charge trapping characteristic with different metal gates are also investigated. A larger memory window was achieved from the TBE-CTF memory with high workfunction metal gate.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1813-1818
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• 2006

We demonstrate a new approach to form gradient hole injection layer (HIL) in organic light-emitting diodes (OLEDs). Single spincoating of hole-injecting conducting polymer compositions with a perfluorinated ionomer results in gradient workfunction through the layer by self-organization, which lead to remarkably efficient single layer polymer light-emitting diodes (PLEDs) (${\sim}21$ cd/A). The device lifetime was significantly improved (${\sim50$ times) compared with the conventional hole injection layer, poly(3,4-ethylenedioxy-thiophene)/polystyrene sulfonate. This solution processed HIL also produced dramatically enhanced luminous efficiency (${\sim}34$ cd/A) in vacuum- deposited green fluorescent OLEDs while the vacuum deposited HIL gave the luminous efficiency of ${\sim}23$ cd/A in the same device structure.

• 대한전기학회논문지
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• 제35권2호
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• pp.67-76
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• 1986

It is observed that an appreciable short-circuit current (Is) flows by the time variation of temperature without applying external field in M1(metal)-P(polymer)-M2(metal)system. In M1-P-M2(A1) system, Is flows in the direction from the electrode(A1) having a lower workfunction to the counter electrode(M1) during heating and its magnitude increases as the thickness of polymer is decreased and as the heating rate is raised. The sign of Is is reversed in lower temperature region (under glass transition temperature) when the direction of temerature variation is changed during heating and cooling. From these experimental results, we can sugest that Is flows in the external short-circuit during the space charge distribution formed around both interfacial surfaces (M1-P and P-M2) is continuously maintained in the non-equilibrium state but not in equilibrium state.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.238-242
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• 2001

In this paper, the current-voltage characteristics of a 4H-SiC MESFET is simulated by using the Atlas Simulation tool. we are able to use the simulator to extract more information about the new material 4H-SiC, including the mobility, velocity-field Curve and the Schottky barrier height. We have enabled and used the new simulator to investigate breakdown Voltage and thus predict operation limitiations of 4H-SiC device. Modeling results indicate that the Breakdown Voltage is 197 V and Current is 100 mA

• 전기전자학회논문지
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• 제19권4호
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• pp.514-519
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• 2015

본 논문에서는 이중 게이트 junctionless MOSFET 의 성능 최적화를 위하여 다중 게이트 형태를 적용하여 평가한다. 금속 게이트들 사이의 일함수가 서로 다르므로 다중 게이트 구조를 적용할 경우 금속게이트 길이에 따라 소스와 드레인 주변의 전위를 조절할 수 있다. 동작 전류와 누설 전류 그리고 동작 전압은 게이트 구조에 의해 조절이 가능하며 이로 인한 동작 특성 최적화가 가능하다. 본 연구에서는 반도체 소자 시뮬레이션을 통하여 junctionless MOSFET 의 최적화를 구현하고 분석하는 연구를 수행 한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.238-242
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• 2001

In this paper, the current-voltage characteristics of a 4H-SiC MESFET is simulated by using the Atlas Simulation tool. we are able to use the simulator to extract more information about the new material 4H-SiC, including the mobility, velocity-field Curve and the Schottky barrier height. We have enabled and used the new simulator to investigate breakdown Voltage and thus predict operation limitations of 4H-SiC device. Modeling results indicate that the Breakdown Voltage is 197 V and Current is 100 mA

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.357-357
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• 2010

Using ab initio density functional theory, we study the structural and electronic properties of interface between Cu surface and highly electron withdrawing hexaazatriphenylene-hexanitrile (HAT-CN) known as an efficient hole injection layer for organic light emitting diodes (OLEDs). We calculate the equilibrium geometries of the interface with different HAT-CN coverages. Usually, some of C-N bonds located at the edge of the HAT-CN molecule are deformed toward Cu atoms resulting in the reconstruction of Cu surface. By analyzing the electron charge and the potential distributions over the interface, we observe the formation of surface dipoles, which modify the work function at the interface. Such dipole formation is attributed to two origins, one of which is a geometrical nature and the other is a bond dipole. The former is related to structural deformation mentioned above, whereas the latter is due to charge transfer between organic and metal surface.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.91-105
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• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.