• Title/Summary/Keyword: Wafer test

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Wafer Map Image Analysis Methods in Semiconductor Manufacturing System (반도체 공정에서의 Wafer Map Image 분석 방법론)

  • Yoo, Youngji;An, Daewoong;Park, Seung Hwan;Baek, Jun-Geol
    • Journal of Korean Institute of Industrial Engineers
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    • v.41 no.3
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    • pp.267-274
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    • 2015
  • In the semiconductor manufacturing post-FAB process, predicting a package test result accurately in the wafer testing phase is a key element to ensure the competitiveness of companies. The prediction of package test can reduce unnecessary inspection time and expense. However, an analysing method is not sufficient to analyze data collected at wafer testing phase. Therefore, many companies have been using a summary information such as a mean, weighted sum and variance, and the summarized data reduces a prediction accuracy. In the paper, we propose an analysis method for Wafer Map Image collected at wafer testing process and conduct an experiment using real data.

Bare Wafer Inspection using a Knife-edge Test

  • Lee, Jun-Ho;Kim, Yong-Min;Kim, Jin-Seob;Yoo, Yeong-Eun
    • Journal of the Optical Society of Korea
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    • v.11 no.4
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    • pp.173-176
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    • 2007
  • We present a very simple and efficient bare-wafer inspection method using a knife-edge test. The wafer front surface and inner structures are inspected simultaneously. The wafer front surface is inspected visually using a knife-edge test while the inner structure is simultaneously inspected by a camera in the infrared region with a single white-light source. This paper presents a laboratory implementation of the test method with some experimental results.

Analytic Map Algorithms of DDI Chip Test Data (DDI 칩 테스트 데이터 분석용 맵 알고리즘)

  • Hwang Kum-Ju;Cho Tae-Won
    • Journal of the Semiconductor & Display Technology
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    • v.5 no.1 s.14
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    • pp.5-11
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    • 2006
  • One of the most important is to insure that a new circuit design is qualified far release before it is scheduled for manufacturing, test, assembly and delivery. Due to various causes, there happens to be a low yield in the wafer process. Wafer test is a critical process in analyzing the chip characteristics in the EDS(electric die sorting) using analytic tools -wafer map, wafer summary and datalog. In this paper, we propose new analytic map algorithms for DDI chip test data. Using the proposed analytic map algorithms, we expect to improve the yield, quality and analysis time.

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Data Qualification of Optical Emission Spectroscopy Spectra in Resist/Nitride/Oxide Etch: Coupon vs. Whole Wafer Etching

  • Kang, Dong-Hyun;Pak, Soo-Kyung;Park, George O.;Hong, Sang-Jeen
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.433-433
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    • 2012
  • As the requirement in patterning geometry continuously shrinks down, the termination of etch process at the exact time became crucial for the success in nano patterning technology. By virtue of real-time optical emission spectroscopy (OES), etch end point detection (EPD) technique continuously develops; however, it also faced with difficulty in low open ratio etching, typically in self aligned contact (SAC) and one cylinder contact (OCS), because of very small amount of optical emission from by-product gas species in the bulk plasma glow discharge. In developing etching process, one may observe that coupon test is being performed. It consumes costs and time for preparing the patterned sample wafers every test in priority, so the coupon wafer test instead of the whole patterned wafer is beneficial for testing and developing etch process condition. We also can observe that etch open area is varied with the number of coupons on a dummy wafer. However, this can be a misleading in OES study. If the coupon wafer test are monitored using OES, we can conjecture the endpoint by experienced method, but considering by data, the materials for residual area by being etched open area are needed to consider. In this research, we compare and analysis the OES data for coupon wafer test results for monitoring about the conditions that the areas except the patterns on the coupon wafers for real-time process monitoring. In this research, we compared two cases, first one is etching the coupon wafers attached on the carrier wafer that is covered by the photoresist, and other case is etching the coupon wafers on the chuck. For comparing the emission intensity, we chose the four chemical species (SiF2, N2, CO, CN), and for comparing the etched profile, measured by scanning electron microscope (SEM). In addition, we adopted the Dynamic Time Warping (DTW) algorithm for analyzing the chose OES data patterns, and analysis the covariance and coefficient for statistical method. After the result, coupon wafers are over-etched for without carrier wafer groups, while with carrier wafer groups are under-etched. And the CN emission intensity has significant difference compare with OES raw data. Based on these results, it necessary to reasonable analysis of the OES data to adopt the pre-data processing and algorithms, and the result will influence the reliability for relation of coupon wafer test and whole wafer test.

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Statistical Design of Experiments and Analysis: Hierarchical Variance Components and Wafer-Level Uniformity on Gate Poly-Silicon Critical Dimension (통계적 실험계획 및 분석: Gate Poly-Silicon의 Critical Dimension에 대한 계층적 분산 구성요소 및 웨이퍼 수준 균일성)

  • Park, Sung-min;Kim, Byeong-yun;Lee, Jeong-in
    • Journal of Korean Institute of Industrial Engineers
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    • v.29 no.2
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    • pp.179-189
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    • 2003
  • Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

Surface Defect Properties of Prime, Test-Grade Silicon Wafers (프라임, 테스트 등급 실리콘 웨이퍼의 표면 결함 특성)

  • Oh, Seung-Hwan;Yim, Hyeonmin;Lee, Donghee;Seo, Dong Hyeok;Kim, Won Jin;Kim, Ryun Na;Kim, Woo-Byoung
    • Korean Journal of Materials Research
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    • v.32 no.9
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    • pp.396-402
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    • 2022
  • In this study, surface roughness and interfacial defect characteristics were analyzed after forming a high-k oxide film on the surface of a prime wafer and a test wafer, to study the possibility of improving the quality of the test wafer. As a result of checking the roughness, the deviation in the test after raising the oxide film was 0.1 nm, which was twice as large as that of the Prime. As a result of current-voltage analysis, Prime after PMA was 1.07 × 10 A/cm2 and Test was 5.61 × 10 A/cm2, which was about 5 times lower than Prime. As a result of analyzing the defects inside the oxide film using the capacitance-voltage characteristic, before PMA Prime showed a higher electrical defect of 0.85 × 1012 cm-2 in slow state density and 0.41 × 1013 cm-2 in fixed oxide charge. However, after PMA, it was confirmed that Prime had a lower defect of 4.79 × 1011 cm-2 in slow state density and 1.33 × 1012 cm-2 in fixed oxide charge. The above results confirm the difference in surface roughness and defects between the Test and Prime wafer.

Effects of Forced Self Driving Function in Silicon Wafer Polishing Head on the Planarization of Polished Wafer Surfaces (실리콘 웨이퍼 연마헤드의 강제구동 방식이 웨이퍼 연마 평탄도에 미치는 영향 연구)

  • Kim, Kyoungjin;Park, Joong-Youn
    • Journal of the Semiconductor & Display Technology
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    • v.13 no.1
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    • pp.13-17
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    • 2014
  • Since the semiconductor manufacturing requires the silicon wafers with extraordinary degree of surface flatness, the surface polishing of wafers from ingot cutting is an important process for deciding surface quality of wafers. The present study introduces the development of wafer polishing equipment and, especially, the wafer polishing head that employs the forced self-driving of installed silicon wafer as well as the wax wafer mounting technique. A series of wafer polishing tests have been carried out to investigate the effects of self-driving function in wafer polishing head. The test results for wafer planarization showed that the LLS counts and SBIR of polished wafer surfaces were generally improved by adopting the self-driven polishing head in wafer polishing stations.

Methods and Sample Size Effect Evaluation for Wafer Level Statistical Bin Limits Determination with Poisson Distributions (포아송 분포를 가정한 Wafer 수준 Statistical Bin Limits 결정방법과 표본크기 효과에 대한 평가)

  • Park, Sung-Min;Kim, Young-Sig
    • IE interfaces
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    • v.17 no.1
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    • pp.1-12
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    • 2004
  • In a modern semiconductor device manufacturing industry, statistical bin limits on wafer level test bin data are used for minimizing value added to defective product as well as protecting end customers from potential quality and reliability excursion. Most wafer level test bin data show skewed distributions. By Monte Carlo simulation, this paper evaluates methods and sample size effect regarding determination of statistical bin limits. In the simulation, it is assumed that wafer level test bin data follow the Poisson distribution. Hence, typical shapes of the data distribution can be specified in terms of the distribution's parameter. This study examines three different methods; 1) percentile based methodology; 2) data transformation; and 3) Poisson model fitting. The mean square error is adopted as a performance measure for each simulation scenario. Then, a case study is presented. Results show that the percentile and transformation based methods give more stable statistical bin limits associated with the real dataset. However, with highly skewed distributions, the transformation based method should be used with caution in determining statistical bin limits. When the data are well fitted to a certain probability distribution, the model fitting approach can be used in the determination. As for the sample size effect, the mean square error seems to reduce exponentially according to the sample size.