• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.128-128
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• 2010

In this study, we investigated the evolution and reduction of the surface roughness during the high-speed chemical dry thinning process of Si wafers. The direct injection of NO gas into the reactor during the supply of F radicals from NF3 remote plasmas was very effective in increasing the Si thinning rate, due to the NO-induced enhancement of the surface reaction, but resulted in the significant roughening of the thinned Si surface. However, the direct addition of Ar and N2 gas, together with NO gas, decreased the root mean square (RMS) surface roughness of the thinned Si wafer significantly. The process regime for the increasing of the thinning rate and concomitant reduction of the surface roughness was extended at higher Ar gas flow rates. In this way, Si wafer thinning rate as high as $20\;{\mu}m/min$ and very smooth surface roughness was obtained and the mechanical damage of silicon wafer was effectively removed. We also measured die fracture strength of thinned Si wafer in order to understand the effect of chemical dry thinning on removal of mechanical damage generated during mechanical grinding. The die fracture strength of the thinned Si wafers was measured using 3-point bending test and compared. The results indicated that chemical dry thinning with reduced surface roughness and removal of mechanical damage increased the die fracture strength of the thinned Si wafer.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.392-392
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• 2010

In this study, high-speed chemical dry thinning process of Si wafer and evolution of surface roughness were investigated. Direct injection of NO gas into the reactor during the supply of F radicals from $NF_3$ remote plasmas was very effective in increasing the Si thinning rate due to the NO-induced enhancement of surface reaction but thinned Si surface became roughened significantly. Addition of Ar gas, together with NO gas, decreased root mean square (RMS) surface roughness of thinned Si wafer significantly. The process regime for the thinning rate enhancement with reduced surface roughness was extended at higher Ar gas flow rate. Si wafer thinning rate as high as $22.8\;{\mu}m/min$ and root-mean-squared (RMS) surface roughness as small as 0.75 nm could be obtained. It is expected that high-speed chemical dry thinning process has possibility of application to ultra-thin Si wafer thinning with no mechanical damage.

• Journal of Welding and Joining
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• v.26 no.1
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• pp.12-16
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• 2008

본 보고에서는 3D 패키징에서 중요한 공정의 하나인 초박막 Si 웨이퍼 Thinning 공정에 대해 간략히 소개하였고, 표면처리에 대해 살펴보았다. 기계적, 특히 전기적 Damage를 줄이기 위한 최적화된 Thinning 공정과 신뢰성 분석 및 평가, 그리고 초박막 웨이퍼 핸들링 방법 등이 시스템적으로 개발되는 것이 중요하다. 칩 소형화 추세와 더불어 3D 패키징 기술이 중요시되는 산업 요구에 맞추어 향후 웨이퍼 Thinning 기술을 포함한 3D 기술의 핵심 공정기술들은 그 중요성이 증대할 것이고, 이에 대한 활발한 연구가 진행되리라 기대한다.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.63-67
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• 2008

3D integration technology has been a major focus of the next generation of IC industries. In this study Si wafer ultra-thinning has been investigated especially for the effect of ultra-thinning on the silicon surface. Wafers were grinded down to $30{\mu}m\;or\;50{\mu}m$ thickness and then grinded only samples were compared with surface treated samples in terms of surface roughness, surface damages, and hardness. Dry polishing or wet etching treatment has been applied as a surface treatment. Surface treated samples definitely showed much less surface damages and better roughness. However, ultra-thinned Si samples have the almost same hardness as a bulk Si wafer.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.81-85
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• 2013

Wafer stacking technology becomes more important for the next generation IC technology. It requires new process development such as TSV, wafer bonding, and wafer thinning and also needs to resolve wafer warpage, power delivery, and thermo-mechanical reliability for high volume manufacturing. In this study, Cu CMP which is the key process for wafer bonding has been studied using Cu CMP and oxide CMP processes. Wafer samples were fabricated on 8" Si wafer using a damascene process. Cu dishing after Cu CMP and oxide CMP was $180{\AA}$ in average and the total height from wafer surface to bump surface was approximately $2000{\AA}$.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.71-78
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• 2012

This paper describes trends in conventional scaling compared with advanced technologies such as 3D integration (3DI) and bumpless through-silicon via (TSV) processes, as well as the characteristics of CMOS (Complementary Metal Oxide Semiconductor) Logic device after thinning the wafers to less than $10{\mu}m$. Each module process including thinning, stacking, and TSV, is optimized for 3D Wafer-on-Wafer (WOW) application. Optimization results are discussed with valuable data in detail. Since vertical wiring of bumpless TSV can be connected directly to the upper and lower substrates by self-alignment, bumps are not necessary when TSV interconnects are used.

• Journal of the Semiconductor & Display Technology
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• v.2 no.1
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• pp.25-29
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• 2003

The fluid flow, mass transfer, heat transfer and film thickness variation during the spin coating process are numerically studied. The model is said to be I-dimensional because radial variations in film thickness, concentration and temperature are ignored. The finite difference method is employed to solve the equations that are simplified using the similarity transformation. In early time, the film thinning is due to the radial convective outflow. However that slows during the first seconds of spinning so the film thinning due to evaporation of solvent becomes sole. The time varing film thickness is analyzed according to the wafer spin speed, the various solvent fraction in the coating liquid, and the various solvent vapor fraction in the bulk of the overlying gas during the spin coating is estimated.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.11 no.1
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• pp.26-32
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• 2012

Polishing is one of the important methods in manufacturing of Si wafers and in thinning of completed device wafers. This study will report the characteristic of wafer according to processing time, machining speed and pressure which have major influence on the abrasion of Si wafer polishing. It is possible to evaluation of wafer abrasion by load cell and infrared temperature sensor. The characteristic of wafer surface according to processing condition is selected to use a result data that measure a pressure, machining speed, and the processing time. This result is appeared by the characteristic of wafer surface in machining condition. Through that, the study cans evaluation a wafer characteristic in variable machining condition. It is important to obtain optimal condition. Thus the optimum condition selection of ultra precision Si wafer polishing using load cell and infrared temperature sensor. To evaluate each machining factor, use a data through each sensor. That evaluation of abrasion according to variety condition is selected to use a result data that measure a pressure, machining speed, and the processing time. And optimum condition is selected by this result.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.921-926
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• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

• Journal of Sensor Science and Technology
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• v.31 no.1
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• pp.36-40
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• 2022

High-power devices, such as LEDs and radars, inevitably generate a large amount of heat, which is the main cause of shortening lifespan, deterioration in performance, and failure of electronic devices. The embedded IC process can be a solution; however, when applied to large-area substrates (larger than 8 in), there is a limit owing to the difficulty in the process after wafer thinning. In this study, an 8-in wafer-level high-power electronic package based on the embedded IC process was implemented with temporary bonding and debonding technology using double-sided thermal release tape. Good heat-dissipation characteristics were demonstrated both theoretically and experimentally. These findings will advance the commercialization of high-power electronic packaging.