• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.341-344
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• 2006

LED chips are produced by cutting the sapphire on which GaN is evaporated. To cut the sapphire wafer into each LED chip, at first the wafer is scribed by diamond tool. To get the sharp groove shape for the nice cutting plane it is important the diamond tool shape, load, etc when the wafer is scribed. Here we tried to simulate the scribing process and get the scribing condition to reduce the wear rate of diamond tool for the sharp groove shape.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2002년도 ICCAS
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• pp.55.4-55
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• 2002

In the semiconductor fabrication, particle contamination is wide-spread and one of major causes to yield loss. Extensive testing has revealed that even careful handling of wafers during processing may cause photo-resist materials to flake off wafer edges. So, to remove the photo-resist at the outer 5mm of wafers, UV(Ultraviolet) rays are exposed. WEE (Wafer Edge Exposure) process station is the system that exposes the wafer edge as prespecified by controlling the positioning mechanism and maintaining the light intensity level In this work, WEE process station has been designed so as to significantly lower the amount of particle contamination which occurs even during the most r...

• 대한기계학회:학술대회논문집
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• 대한기계학회 2003년도 추계학술대회
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• pp.1378-1383
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• 2003

A ferroelectric (called piezoelectric afterwards) wafer has been widely used as a key component of actuators or sensors of a layer type. According to recent researches, the piezoelectric wafer behaves in a nonlinear way under excessive electro-mechanical loadings. In the present paper, one-dimensional constitutive equations for the nonlinear behavior of a piezoelectric wafer are proposed based on the principles of thermodynamics and a simple viscoplasticity theory. The predictions of the developed model are compared with experimental observations.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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• pp.433-435
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• 1987

Thermal reoxidation was carried out to eliminate hole traps at the surface of Si wafer. As the result, the good surface state of wafer was obtained and hole traps were eliminate at the inversion layer. For the evaluation of reoxidation effects. MOS diode was fabricated and its C-Y curve was plotted.

• 한국결정성장학회:학술대회논문집
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• 한국결정성장학회 1996년도 The 9th KACG Technical Annual Meeting and the 3rd Korea-Japan EMGS (Electronic Materials Growth Symposium)
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• pp.88-138
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• 1996

Electronics grew up to the largest industry in the world supported by Si wafer. In near future, the Si wafer may use 300mm in diameter for economic requirement. This size wafer may use to produce large logic chip, 256Mbit DRAM, and other large complex and high density chip. Then, the quality including flatness and crustal characters may be required very high performance. And, their price should be reasonable and high quantity may be required. These requirements should be solve lot of hard problems of crystal growth, wafering mechanical processing and their cost problems. In this presentation, I may discuss following items.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.433-433
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• 2012

As the requirement in patterning geometry continuously shrinks down, the termination of etch process at the exact time became crucial for the success in nano patterning technology. By virtue of real-time optical emission spectroscopy (OES), etch end point detection (EPD) technique continuously develops; however, it also faced with difficulty in low open ratio etching, typically in self aligned contact (SAC) and one cylinder contact (OCS), because of very small amount of optical emission from by-product gas species in the bulk plasma glow discharge. In developing etching process, one may observe that coupon test is being performed. It consumes costs and time for preparing the patterned sample wafers every test in priority, so the coupon wafer test instead of the whole patterned wafer is beneficial for testing and developing etch process condition. We also can observe that etch open area is varied with the number of coupons on a dummy wafer. However, this can be a misleading in OES study. If the coupon wafer test are monitored using OES, we can conjecture the endpoint by experienced method, but considering by data, the materials for residual area by being etched open area are needed to consider. In this research, we compare and analysis the OES data for coupon wafer test results for monitoring about the conditions that the areas except the patterns on the coupon wafers for real-time process monitoring. In this research, we compared two cases, first one is etching the coupon wafers attached on the carrier wafer that is covered by the photoresist, and other case is etching the coupon wafers on the chuck. For comparing the emission intensity, we chose the four chemical species (SiF2, N2, CO, CN), and for comparing the etched profile, measured by scanning electron microscope (SEM). In addition, we adopted the Dynamic Time Warping (DTW) algorithm for analyzing the chose OES data patterns, and analysis the covariance and coefficient for statistical method. After the result, coupon wafers are over-etched for without carrier wafer groups, while with carrier wafer groups are under-etched. And the CN emission intensity has significant difference compare with OES raw data. Based on these results, it necessary to reasonable analysis of the OES data to adopt the pre-data processing and algorithms, and the result will influence the reliability for relation of coupon wafer test and whole wafer test.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.54-54
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• 2009

Ag thick film has been used for electrode materials with the excellent conductivity. Ag electrode is used in screen-printed silicon solar cells as a electrode material. Compared to photolithography and buried-contact technology, screen-printing technology has the merit of fabricating low-priced cells and enormous cells in a few hours. Ag paste consists of Ag powders, vehicles and additives such as frits, metal powders (Pb, Bi, Zn). Frits accelerate the sintering of Ag powders and induce the connection between Ag electrode and Si wafer. Thermophysical properties of frits and reactions among Ag, frits and Si influence on cell performance. In this study, Ag pastes were fabricated with adding different kinds of frits. After Ag pastes were printed on silicon wafer by screen-printing technology, the cells were fired using a belt furnace. The cell parameters were measured by light I-V to determine the short-circuit current, open-circuit voltage, FF and cell efficiency. In order to study the relationship between the reactivity of Ag, frit, Si and the electrical properties of cells, the reaction of frits and Si wafer on was studied with thermal properties of frits. The interface structure between Ag electrode and Si wafer were also measured for understanding the reactivity of Ag, frit and Si wafer. The excessive reactivity of Ag, frit and Si wafer certainly degraded the electrical properties of cells. These preliminary studies suggest that reactions among Ag, frits and Si wafer should optimally be controlled for cell performances.

• 한국윤활학회:학술대회논문집
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• 한국윤활학회 2004년도 학술대회지
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• pp.90-98
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• 2004

Nano/micro-scale studies on friction properties were conducted on Si (100) and three self-assembled monolayers (SAMs) (PFOTC, DMDM, DPDM) coated on Si-wafer by chemical vapor deposition technique. Experiments were conducted at ambient temperature $(24{\pm}1^{\circ}C)$ and humidity $(45{\pm}5\%)$. Nano-friction was evaluated using Atomic Force Microscopy (AFM) in the range of 0-40nN normal loads. In both Si-wafer and SAMs, friction increased linearly as a function of applied normal load. Results showed that friction was affected by the inherent adhesion in Si-wafer, and in the case of SAMs the physical/chemical structures had a major influence. Coefficient of friction of these test samples was also evaluated at the micro-scale using a micro-tribotester. It was observed that SAMs had superior frictional property due to their low interfacial energies. In order to study of the effect of contact area on friction coefficient at the micro-scale, friction was measured for Si-wafer and DPDM against Soda Lime balls (Duke Scientific Corporation) of different radii 0.25 mm, 0.5 mm and 1 mm at different applied normal loads $(1500,\;3000\;and\;4800{\mu}N)$. Results showed that Si-wafer had higher friction coefficient than DPDM. Furthermore, unlike that in the case of DPDM, friction was severely influenced by wear in the case of Si-wafer. SEM evidences showed that solid-solid adhesion to be the wear mechanism in Si-wafer.

• 마이크로전자및패키징학회지
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• 제16권4호
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• pp.23-28
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• 2009

Si 기판의 캐비티 형성이 불필요한 웨이퍼-레벨 MEMS capping 공정을 연구하였다. 4인치 Si 웨이퍼에 Ni 캡을 전기도금으로 형성하고 Ni 캡 rim을 Si 하부기판의 Cu rim에 에폭시 본딩한 후, SnBi debonding 층을 이용하여 상부기판을 Ni 캡 구조물로부터 debonding 하였다. 진공증착법으로 형성한 SnBi debonding 층은 Bi와 Sn 사이의 심한 증기압 차이에 의해 Bi/Sn의 2층 구조로 이루어져 있었다. SnBi 증착 층을 $150^{\circ}C$에서 15초 이상 유지시에는 Sn과 Bi 사이의 상호 확산에 의해 eutectic 상과 Bi-rich $\beta$상으로 이루어진 SnBi 합금이 형성되었다. $150^{\circ}C$에서 유지시 SnBi의 용융에 의해 Si 기판과 Ni 캡 구조물 사이의 debonding이 가능하였다.

• 한국진공학회지
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• 제17권2호
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• pp.165-169
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• 2008

반도체 소자공정에서 균일한 두께의 금속박막을 증착하는 것은 매우 중요하다. 기존의 기판고정식 sputtering 장비로 증착한 indium tin oxide(ITO)박막의 두께 균일도가 $\pm4%\sim\pm5%$ 정도로 중앙부분이 더 두껍다. 방전전극 구조물을 설계하고 제작하여 sputtering되는 물질의 방향을 조절하였다. 개량된 sputtering gun을 사용하여 기판고정식 sputtering 장비에서 4" wafer 내에서 $\pm0.8\sim1.3%$ 정도로 두께 균일도를 증가시켰다. wafer to wafer에서는 $\pm$5.3%에서 $\pm$1.5%로 두께 균일도가 향상되었다. Al박막의 경우 $\pm$1.0% 이내의 두께 균일도를 얻을 수 있었다.