• Proceedings of the Korean Vacuum Society Conference
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• 2009.02a
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• pp.243.1-243.1
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• 2009

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.117-123
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• 2014

Cu through-vias, which can be used as thermal vias or vertical interconnects, were formed using bottom-up electrodeposition filling as well as top-down electrodeposition filling into open via-holes and their microstructures were observed. Solid Cu through-vias without voids could be successfully formed by bottom-up filling as well as top-down filling with direct-current electrodeposition. While chemical-mechanical polishing (CMP) to remove the overplated Cu layer was needed on both top and bottom surfaces of the specimen processed by top-down filling method, the bottomup process has an advantage that such CMP was necessary only on the top surface of the sample.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.1043-1044
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• 2013

• Journal of the Korean Vacuum Society
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• v.4 no.S1
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• pp.102-107
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• 1995

We review the copper CVD line, via fill properties, and CMP line resistance. With CVD, trenches and vias with high aspect ratio(above 3) can be filled completely. Sputtering-reflow technique, a new method to filling copper into lines, is also reviewed to compare the CVD process.

• ETRI Journal
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• v.35 no.3
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• pp.534-537
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• 2013

A compact monopole antenna excited by a conductor-backed coplanar waveguide (CBCPW) is developed for wireless USB dongle applications. The proposed antenna has a compact dimension of $14mm{\times}47.4mm{\times}3.5mm$, which is suitable for a USB dongle housing. A slotted elliptical patch and a CBCPW with vertical vias are employed to achieve a further size reduction and an improved impedance bandwidth. The measurement result demonstrates that the fabricated antenna resonates from 2.25 GHz to 10.9 GHz, which covers all of the important wireless communication bands, including WiBro (2.3 GHz to 2.4 GHz), Bluetooth (2.4 GHz to 2.484 GHz), WiMAX (2.5 GHz to 2.7 GHz and 3.4 GHz to 3.6 GHz), satellite DMB (2.605 GHz to 2.655 GHz), 802.11b/g/a WLAN (2.4 GHz to 2.485 GHz and 5.15 GHz to 5.825 GHz), and ultra-wideband (3.1 GHz to 10.6 GHz) services. The radiation characteristics of the proposed antenna when attached to a laptop are tested to investigate the influence of the keypad and the LCD panel of the laptop.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.371-374
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• 2005

This paper presents the design and fabrication of a cost effective and broad band 8$\times$8 stacked patch array antenna which are backed by a metal cavity operating at 400Hz based on 4 layers LTCC technology. Gain of antenna can be enhanced by using a metal cavity, which can be easily implemented by using LTCC substrates and vias. The broadband performance can be obtained by varying the dimension of patch and the number of layers. Furthermore, to keep the feeding network as smal1 as possible and reduce radiation from feeding network a mirrored patch orientation and embedded micro strip line are adopted, The fabricated antenna is $40\times45\times0.4$ $mm^3$in size. It shows gain 20.4dBi, beam width 10.7deg and impedance bandwidth of l0dE return loss 3.35GHz (40.9$\sim$44.25 GHz), which is about 8% of a center frequency.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.2
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• pp.37-42
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• 2001

The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Journal of the Optical Society of Korea
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• v.18 no.5
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• pp.531-537
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• 2014

Through-silicon vias (TSVs) are fine, deep holes fabricated for connecting vertically stacked wafers during three-dimensional packaging of semiconductors. Measurement of the TSV geometry is very important because TSVs that are not manufactured as designed can cause many problems, and measuring the critical dimension (CD) of TSVs becomes more and more important, along with depth measurement. Applying white-light scanning interferometry to TSV measurement, especially the bottom CD measurement, is difficult due to the attenuation of light around the edge of the bottom of the hole when using a low numerical aperture. In this paper we propose and demonstrate four bottom CD measurement methods for TSVs: the cross section method, profile analysis method, tomographic image analysis method, and the two-dimensional Gaussian fitting method. To verify and demonstrate these methods, a practical TSV sample with a high aspect ratio of 11.2 is prepared and tested. The results from the proposed measurement methods using white-light scanning interferometry are compared to results from scanning electron microscope (SEM) measurements. The accuracy is highest for the cross section method, with an error of 3.5%, while a relative repeatability of 3.2% is achieved by the two-dimensional Gaussian fitting method.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.04a
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• pp.27-34
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• 2001

The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• ETRI Journal
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• v.36 no.6
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• pp.931-941
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• 2014

Many methodologies for clock mesh networks have been introduced for two-dimensional integrated circuit clock distribution networks, such as methods to reduce the total wirelength for power consumption and to reduce the clock skew variation through consideration of buffer placement and sizing. In this paper, we present a methodology for clock mesh to reduce both the clock skew and the total wirelength in three-dimensional integrated circuits. To reduce the total wirelength, we construct a smaller mesh size on a die where the clock source is not directly connected. We also insert through-silicon vias (TSVs) to distribute the clock signal using an effective clock TSV insertion algorithm, which can reduce the total wirelength on each die. The results of our proposed methods show that the total wirelength was reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. These advantages are possible through increasing the buffer area by 2.49% on the benchmark circuits.