• Title/Summary/Keyword: Vertical transistor

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A Study on the Characteristics of the Vertical PNP transistor that improves the starting current (기동 전류를 개선한 수직 PNP 트랜지스터의 특성에 관한 연구)

  • Lee, Jung-Hwan
    • Journal of Korea Society of Industrial Information Systems
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    • v.21 no.1
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    • pp.1-6
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    • 2016
  • In this paper, we introduce the characteristics of a vertical PNP transistor that improves start current by decreasing quiescent current with suppressing the parasitic transistor. In order to suppress the parasitic effect, we designed a vertical PNP transistor which suppresses parasitic PNP transistor by using the "DN+ links" without changing the circuit and made a LDO regulator using a standard IC processor. HFE of the fabricated parasitic PNP transistor decreased from conventional 18 to 0.9. Starting current of the LDO regulator made of the vertical PNP transistor using the improved "DN+ linked" structure is reduced from the conventional starting current of 90mA to 32mA. As the result, we developed a LDO regulator which consumes lower power in the standby state.

Vertical Type Organic Transistors and Flexible Display Applications

  • Kudo, Kazuhiro
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08a
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    • pp.168-169
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    • 2007
  • Organic transistors are promising in the future development of active devices for flexible, low-cost and large-area photoelectric devices. However, conventional organic field-effect transistors have lowspeed, low-power, and relatively high operational voltage. Vertical type transistors show high-speed and high-current characteristics and are suitable for driver elements of flexible displays.

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New Fabrication Process of Vertical-Type Organic TFTs for High-Current Drivers

  • Kudo, Kazuhiro;Nakamura, Masakazu
    • 한국정보디스플레이학회:학술대회논문집
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    • 2009.10a
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    • pp.307-309
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    • 2009
  • We have fabricated vertical-type organic transistors (static induction transistors; SITs) with built-in nano-triode arrays formed in parallel by a colloidal-lithography technique. Using this technique, we could fabricate a microstructure in a lateral direction within a large-scale organic device without relying on photolithography. The organic transistor showed low operating voltages, high current output, and large transconductance.

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Characteristics of vertical type organic light emitting transistor using $C_{60}$ as a N-type semiconductor material and MEH-PPV as an emitting polymer

  • Lee, Jung-Bae;Jin, Hee-Suk;Oh, Se-Young
    • 한국정보디스플레이학회:학술대회논문집
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    • 2008.10a
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    • pp.443-445
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    • 2008
  • We have fabricated vertical type organic thin film transistor using $C_{60}$ as a n-type active material to improve the problems of conventional OTFTs. In general, it can be argued that the characteristics of organic transistor were influenced by carrier mobility and density. We have used several kinds of metals as source and gate electrodes to optimize the device characteristics using $C_{60}$. In addition, we have examined the feasibility of fabrication of organic light-emitting transistor (OLET) using MEH-PPV as an emission layer.

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High Quality Vertical Silicon Channel by Laser-Induced Epitaxial Growth for Nanoscale Memory Integration

  • Son, Yong-Hoon;Baik, Seung Jae;Kang, Myounggon;Hwang, Kihyun;Yoon, Euijoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.2
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    • pp.169-174
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    • 2014
  • As a versatile processing method for nanoscale memory integration, laser-induced epitaxial growth is proposed for the fabrication of vertical Si channel (VSC) transistor. The fabricated VSC transistor with 80 nm gate length and 130 nm pillar diameter exhibited field effect mobility of $300cm^2/Vs$, which guarantees "device quality". In addition, we have shown that this VSC transistor provides memory operations with a memory window of 700 mV, and moreover, the memory window further increases by employing charge trap dielectrics in our VSC transistor. Our proposed processing method and device structure would provide a promising route for the further scaling of state-of-the-art memory technology.

Effect of Thermal Heat Treatment on the Characteristics of Vertical Type Organic Thin Film Transistor Using Alq3 as Active Layer and Its Application for OLET

  • Oh, Se-Young;Kim, Young-Do;Hwang, Sun-Kak
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08a
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    • pp.644-647
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    • 2007
  • We have fabricated vertical type organic thin film transistor using tris-8-hydroxyquinoline aluminum $(Alq_3)$. The effects of the growth control of $Alq_3$ thin layer on the grain structure and the flatness of film surface have been investigated. In addition, we have fabricated light emitting transistor and then investigated electroluminescent properties.

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DC and RF Analysis of Geometrical Parameter Changes in the Current Aperture Vertical Electron Transistor

  • Kang, Hye Su;Seo, Jae Hwa;Yoon, Young Jun;Cho, Min Su;Kang, In Man
    • Journal of Electrical Engineering and Technology
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    • v.11 no.6
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    • pp.1763-1768
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    • 2016
  • This paper presents the electrical characteristics of the gallium nitride (GaN) current aperture vertical electron transistor (CAVET) by using two-dimensional (2-D) technology computer-aided design (TCAD) simulations. The CAVETs are considered as the alternative device due to their high breakdown voltage and high integration density in the high-power applications. The optimized design for the CAVET focused on the electrical performances according to the different gate-source length ($L_{GS}$) and aperture length ($L_{AP}$). We analyze DC and RF parameters inducing on-state current ($I_{on}$), threshold voltage ($V_t$), breakdown voltage ($V_B$), transconductance ($g_m$), gate capacitance ($C_{gg}$), cut-off frequency ($f_T$), and maximum oscillation frequency ($f_{max}$).

Design of a high speed and high intergrated ISL(Intergrated Schottky Logic) using a merged transistor (병합트랜지스터를 이용한 고속, 고집적 ISL의 설계)

  • 장창덕;이용재
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 1999.05a
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    • pp.415-419
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    • 1999
  • Many bipolar logic circuit of conventional occurred problem of speed delay according to deep saturation state of vertical NPN Transistor. In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. The structure of Gate consists of the vertical NPN Transistor, substrate and Merged PNP Transistor. In the result, we fount that tarriers which are coming into intrinsic Base from Emitter and the portion of edge are relatively a lot, so those make Base currents a lot and Gain is low with a few of collector currents because of cutting the buried layer of collector of conventional junction area. Merged PNP Transistor's currents are low because Base width is wide and the difference of Emitter's density and Base's density is small. we get amplitude of logic voltage of 200mv, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26nS in AC characteristic output of Ring-Oscillator connected Gate.

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Structure Effects on Organic Thin-Film Transistor Properties of Dinaphthyl Substituted Pentacene Derivatives

  • Son, Ji-Hee;Kang, In-Nam;Oh, Se-Young;Park, Jong-Wook
    • Bulletin of the Korean Chemical Society
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    • v.28 no.6
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    • pp.995-998
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    • 2007
  • Pentacene moiety has been widely studied in Organic Thin-Film Transistor (OTFT) device as a channel layer because of high carrier mobility. In this study, we have fabricated vertical type Organic Static Induction Transistors (SITs) using pentacene, 6,13-Dinaphthalen-1-ly-Pentacene (1-DNP, 3), and 6,13-Dinaphthalen-2- ly-Pentacene (2-DNP, 4). 1-DNP and 2-DNP have same naphtyl group with pentacene, but different linked position and spatial arrangement. We have checked the static characteristics of materials in vertical type SITs device. We found that pentacene has as on/off ratio of 14.56, 1-DNP and 2-DNP shows as on/off ratio of 36.58 and 6.61 at VDS = 2V in SIT, respectively.

Fabrication of Vertical Organic Junction Transistor by Direct Printing Method

  • Shin, Gunchul;Kim, Gyu-Tae;Ha, Jeong Sook
    • Bulletin of the Korean Chemical Society
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    • v.35 no.3
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    • pp.731-736
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    • 2014
  • An organic junction transistor with a vertical structure based on an active layer of poly(3-hexylthiophene) was fabricated by facile micro-contact printing combined with the Langmuir-Schaefer technique, without conventional e-beam or photo-lithography. Direct printing and subsequent annealing of Au-nanoparticles provided control over the thickness of the Au electrode and hence control of the electrical contact between the Au electrode and the active layer, ohmic or Schottky. The junction showed similar current-voltage characteristics to an NPN-type transistor. Current through the emitter was simply controllable by the base voltage and a high transconductance of ~0.2 mS was obtained. This novel fabrication method can be applied to amplifying or fast switching organic devices.