• Korean Journal of Materials Research
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• v.17 no.7
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• pp.347-351
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• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.7 no.3
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• pp.521-527
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• 1995

The average particle deposition velocity toward a vertical wafer surface in a vertical airflow chamber was measured by a wafer surface scanner(PMS Model SAS-3600). Polystyrene latex(PSL) spheres with diameters between 0.3 and $0.8{\mu}m$ were used. To examine the effect of the airflow velocity on the deposition velocity, experiments were conducted for three vertical airflow velocities ; 20, 30, 50cm/s. Experimental data of particle deposition velocity were compared with those given by prediction model suggested by Liu and Ahn(1987).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1237-1241
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• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.379-380
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• 2008

This paper presents a wafer-level package using a Dry Film Resist(DFR) for RF MEMS devices. Vertical interconnection is made through the hole formed on the glass cap. Bonding using the DFR has not only less effects on the surface roughness but also low process temperature. We used DFR as adhesive polymer and made the vertical interconnection through Au electroplating. Therefore, we developed a wafer-level package that is able to be used in RF MEMS devices and vertical interconnection.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.2023-2025
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• 2002

We have fabricated a novel vertical trench-Hall device sensitive to the magnetic field parallel to the sensor chip surface. The vertical trench-Hall device is built on SOI wafer which is produced by silicon direct bonding technology using bulk micromachining, where buried $SiO_2$ layer and surround trench define active device volume. Sensitivity up to 350 V/AT is measured.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.825-831
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• 2006

As an increase of chip complexity and level of chip integration, chip input/output (I/O) pad pitches are also drastically reduced. With arrival of high complexity SoC (System on Chip) and SiP (System in Package) products, conventional horizontal type probe card showed its limitation on probing density for wafer level test. To enhance probing density, we proposed new vertical type probe card that has the $70{\mu}m$ probe needle with tungsten wire in $80{\mu}m$ micro-drilled hole in ceramic board. To minimize alignment error, micro-drilling conditions are optimized and epoxy-hardening conditions are also optimized to minimize planarity changes. To apply wafer level test for target devices (T5365 256M SDRAM), designed probe card was characterized by probe needle tension for test, contact resistance measurement, leakage current measurement and the planarity test. Compare to conventional probe card with minimum pitch of $50{\sim}125{\mu}m\;and\;2\;{\Omega}$ of average contact resistance, designed probe card showed only $22{\mu}$ of minimum pitch and $1.5{\Omega}$ of average contact resistance. And also, with the nature of vertical probing style, it showed comparably small contact scratch and it can be applied to bumping type chip test.

• Journal of the Korean Ceramic Society
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• v.46 no.1
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• pp.30-34
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• 2009

A Sand blasting technology has been used to address via and trench processing of glass wafer of optic semiconductor packaging. Manufactured sand blast that is controlled by blast nozzle and servomotor so that 8" wafer processing may be available. 10mm sq test device manufactured by Dry Film Resist (DFR) pattern process on 8" glass wafer of $500{\mu}m's$ thickness. Based on particle pressure and the wafer transfer speed, etch rate, mask erosion, and vertical trench slope have been analyzed. Perfect 500 um tooling has been performed at 0.3 MPa pressure and 100 rpm wafer speed. It is particle pressure that influence in processing depth and the transfer speed did not influence.

• Proceedings of the KIEE Conference
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• 2007.11a
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• pp.148-149
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• 2007

We present the design and fabrication prcoess of a two-axis tilting micromirror device driven by the electrostatic vertical comb actuator. A high aspect-ratio comb actuator is fabricated by multiple DRIE process in order to achieve large scan angle. The proposed fabrication process enables a mirror to be fabricated on the wafer-scale. By bonding a double-side polished (DSP) wafer and a silicon-on-insulator (SOI) wafer together, all actuators on the wafer are completely hidden under the reflectors. Nickel lines are embedded on a Pyrex wafer for the electrical access to numerous electrodes of mirrors. An anodic bonding step is implemented to contact electrical lines with ail electrodes on the wafer at a time. The mechanical angle of a fabricated mirror has been measured to be 1.9 degree and 1.6 degree, respectively, in the two orthogonal axes under driving voltages of 100 V. Also, a $8{\times}8$ array of micromirrors with high fill-factor of 70 % is fabricated by the same fabrication process.

• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.1
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• pp.175-183
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• 1994

To investigate thermophoretic effect on particle deposition, average deposition velocity toward a horizontal wafer surface in vertical airflow is measured keeping the wafer surface temperature different from the surrounding air temperature. In the present measurement, the temperature difference is maintained in the range from -10 to $4^{\circ}$ C Polystyrene latex (PSL) spheres of diameter between 0.3 and 0.8 .mu.m are used for the experiment. The number of particles deposited on a wafer surface is estimated from the measurements using a wafer surface scanner (PMS SAS-3600). Experimental data are compared with prediction model results.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.793-796
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• 2005

In this paper, we propose a method which can improve uniformity of a miniaturized electron beam array for inspection of very small pattern with high speed using vertical interconnection. This method enables the individual control of columns so that it can reduce the deviation of beam current, beam size, scan range and so on. The test device that used vertical interconnection method was fabricated by multiple wafer bonding and metal reflow. Two silicon and one glass wafers were bonded and metal interconnection by melting of electroplated AuSn was performed. The contact resistance was under $10{\Omega}$.