• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.4
• /
• pp.31-43
• /
• 1999

The main goal of this paper is to design a high performance SVP(Stack based Video Processor) for network applications. The SVP is a comprehensive scheme; 'better' in the sense that it is an optimal selection of previously proposed enhancements of a stack machine and a video processor. This can process effectively object-based video data using a S-RISC(Stack-based Reduced Instruction Set Computer) with a semi -general-purpose architecture having a stack buffer for OOP(Object-Oriented Programming) with many small procedures at running programs. And it includes a vector processor that can improve the MPEG coding speed. The vector processor in the SVP can execute advanced mode motion compensation, motion prediction by half pixel and SA-DCT(Shape Adaptive-Discrete Cosine Transform) of MPEG-4. Absolutors and halfers in the vector processor make this architecture extensive to a encoder. We also designed a VLSI stack-oriented video processor using the proposed architecture of stack-oriented video decoding. It was designed with O.5$\mu\textrm{m}$ 3LM standard-cell technology, and has 110K logic gates and 12 Kbits SRAM internal buffer. The operating frequency is 50MHz. This executes algorithms of video decoding for QCIF 15fps(frame per second), maximum rate of VLBV(Very Low Bitrate Video) in MPEG-4.

• Proceedings of the IEEK Conference
• /
• 2004.08c
• /
• pp.477-481
• /
• 2004

High Quality CD, OAT audio requires that large amount of data. Currently, multi channel preference has been rapidly propagated among latest users. The MPEG(Moving Picture Expert Group) is provides data compression technology of sound and image system. The MPEG standard provides multi channel and 5.1 sounds, using the same audio algorithm as MPEG-l. And MPEG-2 audio is forward and backward compatible. The MDCT (Modified Discrete Cosine Transform) is a linear orthogonal lapped transform based on the idea of TDAC(Time Domain Aliasing Cancellation). In this paper, we proposed the micro-program type vector processor architecture a benefit in MDCT/IMDCT of MPEG-II AAC. And it's reduced operating coefficient by overlapped area to bind. To compare original algorithm with optimized algorithm that cosine coefficient reduced $0.5\%$multiply operating $0.098\%$ and add operating 80.58\%$. Algorithm test is used C-language then we designed hardware architecture of micro-programmed method that applied to optimized algorithm. This processor is 20MHz operation 5V.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
• /
• v.5B no.4
• /
• pp.350-357
• /
• 2005

This paper presents a mechanical sensorless vector-controlled system with parameter identification by the aid of image processor. Based on the flux observer and the model reference adaptive system method, the proposed sensorless system includes rotor speed estimation and stator resistance identification using flux errors. Since the mathematical model of this system is constructed in a synchronously rotating reference frame, a linear model is easily derived for analyzing the system stability, including motor operating state and parameter variations. Because it is difficult to identify rotor resistance simultaneously while estimating rotor speed, a low-accuracy image processor is used to measure the mechanical axis position for calculating the rotor speed at a steady-state operation. The rotor resistance is identified by the error between the estimated speed using the estimated flux and the calculated speed using the image processor. Finally, the validity of this proposed system has been proven through experimentation.

• The Transactions of the Korea Information Processing Society
• /
• v.5 no.8
• /
• pp.1985-1996
• /
• 1998

A parallelising algorithm for partitioning and mapping methods of matrix/vector multiplication into linear processor array/VLW simulator is presented in this paper. First we discuss the mapping methods for input matrix or vector into the arbitrarily size of processor arrays. Then, we show partitioning the algorithmss of the large size of computational problem into the size of the processor array. We execute the algorithm on VLIW simuhator and show to effectiviness of algorithm. The result which we achived better parallelising performance on our VLIW simulator dsign than on linear processor array.

• Journal of the Korea Society of Computer and Information
• /
• v.5 no.3
• /
• pp.16-28
• /
• 2000

In this paper, we implemented by describing a pipeline processor using a HDL in functional level, simulated and verified it's operation. When simulating a implemented processor. We first specify assembly instruction that is Performed in the processor. entered by programming using the instruction sets at the experimental framework. Thus, the procedure that is presented in this paper can easily identify and verify the purpose for implementation and operation of a system by using test vector. Also, it was possible that exactly simulate a system. The method was comfortable that document a system operation to implement.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.329-332
• /
• 1999

Currently, the most important technology is compression methods in the multimedia society. In audio compression, the method using human auditory nervous property is used. This method using psychoacoustical model is applied to perceptual audio coding, because human's audibility is limited. MPEG-II AAC(Advanced Audio Coding) is the most advanced coding scheme that is of benefit to high quality audio coding. The compression ratio is 1.4 times compared with MPEG-I layer-III. In this paper, the vector processor for MDCT/IMDCT(Modified Discrete Cosine Transform /Inverse Modified Discrete Cosine Transform) of MPEG-II AAC is designed.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.23 no.3
• /
• pp.340-344
• /
• 1986

This paper shows that we can design a vector-coordinate rotation processor and obtain the approximate evaluations of sine and cosine based upon the use of residue number systems. The algorithm results in the considerable improvement of the computation speed when compared to CORDIC algorithm. The results from computer simulation show that the mean error of sine and cosine is 0.0025 and the mean error of coordinate rotation arithmatic is 0.65. Also, the proposed processor has the efficiency for the design and fabrication of integrated circuit, because it consists of the array of idecntially structured look-up tables.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.30B no.1
• /
• pp.1-9
• /
• 1993

In recent days high perfermance graphic operation is needed, since computer graphics is widely used for computer-aided design and simulator using high resolution graphic card. In this paper a graphic accelerator is designd with the functions of graphic primitives generation and geometrical transformations. 1-D Systolic Array Processor for Matris Vector operation is designed and used in main ALU of a graphic accelerator, since these graphic algorithms have comonon operation of Matris Vector. Conclusively, in case that the resolution of graphic domain is 800$\times$600, and 33.3nsec operator is used in a graphic accelerator, 29732 lines per second and approximately 6244 circles per second is generated.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.10
• /
• pp.46-52
• /
• 2009

A Multi-Core/Multi-Thread architecture is adopted for the Shader processor to enhance the processing performance. The Shader processor is designed to utilize its processing core IP for multiple purposes, such as Vertex-Shading, Rasterization, Pixel-Shading, etc. In this paper, we propose a 'Rasterization based on Vector Algorithm' that makes parallel pixels processing possible with Multi-Core and Multi-Thread architecture on the Shader Core. The proposed algorithm takes only 2% operation counts of the Scan-Line Algorithm and processes pixels independently.

• Proceedings of the KIPE Conference
• /
• 1999.07a
• /
• pp.469-471
• /
• 1999

In this paper, the method of Space-Vector Pulse Width Modulation(SVPWM) with Fuzzy Logic Regulator(FLR) is proposed. In a conventional SVPWM, the procedures of phase transformation and choosing PWM patterns are complex. So, it should be implemented with high performance processor like Digital Signal Processor(DSP). In order to reduce a calculation burden, a proposed system adopts FLR. Using a linguistic contro strategy based on expert knowledge, FLR relieves the processor from a heavy computations. In simulations, the proposed system is validated.