• Journal of Digital Convergence
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• v.11 no.2
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• pp.287-297
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• 2013

In this paper, we propose an efficient variable-length radix-8/4/2 FFT architecture for OFDM systems. The FFT processor is based on radix-8 FFT algorithm and also supports radix-4 or radix-2 FFT computation. We are using efficient "In-place" memory access method to maintain conflict-free data access and minimize memory size. Also we replace a very large lookup table with a twiddle factor generator which consumes less area then a ROM-based lookup table. The proposed FFT processor performs variable-length FFT including 64, 256, 512, 1024, 2048, 4096 and 8192 points which cover all the required FFT lengths used in 802.11a, 802.16a, DAB, DVB-T, VDSL and ADSL.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.393-396
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• 2009

This paper describes a design of variable-length FFT/IFFT processor for OFDM-based communication systems. The designed FFT/IFFT processor adopts the in-place single-memory architecture, and uses a hybrid structure of radix-4 and radix-2 DIF algorithms to accommodate FFT lengths of $N=64{\times}2^k$ ($0{\leq}k{\leq}7$). To achieve both memory size reduction and the improved SQNR, a two-step conditional scaling technique is devised, which conditionally scales the intermediate results of each computational stage. The performance analysis results show that the average SQNR's of 64~8,192-point FFT's are over 60-dB. The processor synthesized with a $0.35-{\mu}m$ CMOS cell library can operate with 75-MHz@3.3-V clock, and 64-point and 8,192-point FFT's can be computed in $2.55-{\mu}s$ and $762.7-{\mu}s$, respectively, thus it satisfies the specifications of wireless LAN, DMB, and DVB systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2A
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• pp.209-215
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• 2010

This paper describes a design of variable-length FFT/IFFT processor (VL_FCore) for OFDM-based multi-standard communication systems. The VL_FCore adopts in-place single-memory architecture, and uses a hybrid structure of radix-4 and radix-2 DIF algorithms to accommodate various FFT lengths in the range of $N=64{\times}2^k\;(0{\leq}k{\leq}7)$. To achieve both memory size reduction and the improved SQNR, a two-step conditional scaling technique is devised, which conditionally scales the intermediate results of each computational stage. The performance analysis results show that the average SQNR's of 64~8,192-point FFT's are over 60-dB. The VL_FCore synthesized with a $0.35-{\mu}m$ CMOS cell library has 23,000 gates and 32 Kbytes memory, and it can operate with 75-MHz@3.3-V clock. The 64-point and 8,192-point FFT's can be computed in $2.25-{\mu}s$ and $762.7-{\mu}s$, respectively, thus it satisfies the specifications of various OFDM-based systems.

• Journal of Advanced Navigation Technology
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• v.24 no.2
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• pp.85-91
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• 2020

Recently, a multi-mode radar system was designed for efficient operation of unmanned aerial vehicles (UAVs) in various environments, which has the advantage of being able to integrate and utilize methods of the pulse Doppler (PD) radar and the frequency modulated continuous wave (FMCW) radar. For the range detection part of the multi-mode radar signal processor (RSP), the hardware structure using the FFT processor and the IFFT processor is required to be designed in a way that improves efficiency on the area side. In addition, given the radar application environment that requires a variety of distance resolutions, FFT processors need to support variable-length operations. In this paper, the FFT processor and IFFT processor in multi-mode RSP range estimation are designed and proposed as hardware for a single FFT processor that supports variable length operation of 16-1024 points. The proposed FFT processor designed in hardware description language (HDL) and can be implemented with 7,452 logic elements and 5,116 registers.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.11 no.1
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• pp.76-81
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• 2012

Ultrasonic metal welding is one of the welding methods which welds metal by applying high frequency vibrational energy into specific area at constant pressure, avaliable in room temperature and low temperature. Ultrasonic metal welder is consisted of power supply, transducer, booster, and horn. Precise designing is required since each parts' shape, length and mass can affect driving frequency and vibration mode. This paper focused to horn design, its length L was set to 62mm by calculating vibration equation. By performing modal analysis with various shape variable b times integer, when length of b is 30mm the output was 39,599Hz at 10th mode. Also by performing harmonic response analysis, the frequency response result was 39,533Hz, which was similar to modal analysis result. In order to observe the designed horn's performance, about 4,000 voltage data was obtained from a light sensor and was analyzed by FFT analysis using Origin Tool. The result RMS amplitude was approximately 8.5${\mu}m$ at 40,000Hz, and maximum amplitude was 12.3${\mu}m$. Therefore, it was verified that the ultrasonic metal welding horn was optimally designed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.87-95
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• 2009

In this paper, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed scalable FFT processor can support the variable length of 64, 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate4eve1 circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 59% and 39%, respectively, compared with those of the 4-channel radix-2 single-path delay feedback (R2SDF) FFT processor. Also, compared with 4-channel radix-2 MDC (R2MDC) FFT processor, it is confirmed that the gate count and memory size are reduced by 16.4% and 26.8, respectively.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.2
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• pp.97-102
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• 2010

In this paper, an area-efficient FFT processor is proposed for IEEE 802.16e mobile WiMax systems. The proposed scalable FFT processor can support the variable length of 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput. The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 16% and 27%, respectively, compared with those of the 4-channel radix-2 MDC (R2MDC) FFT processor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.621-622
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• 2017

In this paper, a low-complexity FFT processor is proposed for narrow-band interference signal cancellation based array antenna. The proposed FFT pocessor can support the variable length of 64, 128 and 512. By reducing number of non-tirval multipliers with mixed radix-4/2/4/2/4/2 algorithm and flexible multi-path delay commutator(MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased. The proposed FFT processor was designed in Xilinx system generator and Implemented with Xilinx Virtex-7 FPGA. With the proposed architecture, the number of slices for the processor is 11454, and the number of DSP48s is 194.

• Tribology and Lubricants
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• v.33 no.6
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• pp.303-308
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• 2017

Most automobile tire companies have not yet considered the geometric information of a road at the design stage of a tire because the topographical characterization of a road surface is very difficult owing to its vastness and randomness. A road surface shows variable surface roughness values according to magnification, and thus, the contact force between the road and tire significantly fluctuates with respect to the scale. In this study, we make an attempt to define a representative value for surface topographical information at multi-scale levels. To represent surface topography, we use a statistical method called power spectral density (PSD). We use the fast Fourier transform (FFT) and PSD to analyze the height profiles of a random surface. The FFT and PSD of a surface help in obtaining a fractal dimension, which is a representative value of surface topography at all length scales. We develop three surfaces with different fractal dimensions. We use finite element analysis (FEA) to observe the contact forces between a tire and the road surfaces with three different fractal dimensions. The results from FEA reveal that an increase in the fractal dimension decreases the contact length between the tire and road surfaces. On the contrary, the average contact force increases. This result indicates that designing and manufacturing a tire considering the fractal dimension of a road makes safe driving possible, owing to the improvement in service life and braking performance of the tire.

• Journal of Advanced Navigation Technology
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• v.21 no.6
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• pp.659-665
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• 2017

In this paper, a low complexity fast Fourier transform(FFT) processor is proposed for multiple input multiple output(MIMO) systems. The IEEE 802.11ac standard has been adopted along with the demand for a system capable of high channel capacity and Gbps transmission in order to utilize various multimedia services using a wireless LAN. The proposed scalable FFT processor can support the variable length of 64, 128, 256, and 512 for 8x8 antenna configuration as specified in IEEE 802.11ac standard with MIMO-OFDM scheme. By reducing the required number of non-trivial multipliers with mixed-radix(MR) and multipath delay commutator(MDC) architecture, the complexity of the proposed FFT processor was dramatically decreased. Implementation results show that the proposed FFT processor can reduced the logic gate count by 50%, compared with the radix-2 SDF FFT processor. Also, compared with the 8-channel MR-2/2/2/4/2/4/2 MDC processor and 8-channel MR-2/2/2/8/8 MDC processor, it is shown that the gate count is reduced by 18% and 17% respectively.