• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.251-265
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• 2001

As the device scaling proceeds, the operating voltage(VDD) of giga-bit DRAMs is expected to be reduced to 1.5V or down, fir improving the device reliability and reducing the power dissipation. Therefore the low-voltage circuit design techniques are required to implement giga-bit DRAMs. In this work, state-of-art low-voltage DRAM circuit techniques are reviewed, and four kinds of low-voltage circuit design techniques are newly proposed for giga-bit DRAMs. Measurement results of test chips and SPICE simulation results are presented for the newly proposed circuit design techniques, which include a hierarchical negative-voltage word-line driver with reduced subthreshold leakage current, a two-phase VBB(Back-Bias Voltage) generator, a two-phase VPP(Boosted Voltage) generator and a bandgap reference voltage generator.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.2
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• pp.73-78
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• 2020

In this study, a novel reactive power control scheme is proposed to supply stable reactive power to the distribution line by compensating a ripple voltage of DC link. In a single-phase system, a magnitude of second harmonic is inevitably generated in the DC link voltage, and this phenomenon is further increased when the capacity of DC link capacitor decreases. Reactive power control was performed by controlling the d-axis current in the virtual synchronous reference frame, and the voltage control for maintaining the DC link voltage was implemented through the q-axis current control. The proposed method for compensating the ripple voltage was classified into three parts, which consist of the extraction unit of DC link voltage, high pass filter (HPF), and time delay unit. HPF removes an offset component of DC link voltage extracted from integral, and a time delay unit compensates the phase leading effect due to the HPF. The compensated DC voltage is used as feedback component of voltage control loop to supply stable reactive power. The performance of the proposed algorithm was verified through simulation and experiments. At DC link capacitance of 375 uF, the magnitude of ripple voltage decreased to 8 Vpp from 74 Vpp in the voltage control loop, and the total harmonic distortion of the current was improved.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.4
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• pp.123-127
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• 2021

Millimeter-wave tracking radars should be operated in various environmental restrictions, thus they demand more computing power and smaller size compared to conventional tracking radars. This paper presents the design and implementation of the compact power supply for millimeter-wave tracking radar applications. To meet requirements of low voltage/high current and voltage accuracy for FPGA/DSP digital circuits, Point of Load (POL) converters are used in order to enhance power density and system efficiency. LDO (Low Dropout) is applied for the output voltage under the light load condition, then the single-input-multi-output power supply with max power of 375 W and 8 outputs is developed. The proposed power supply achieves output voltage accuracy of ±2 % and noise level of <50 mVpp % under full load conditions.

• Journal of IKEEE
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• v.28 no.1
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• pp.78-89
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• 2024

PMIC chips based on a BCD process used in automotive semiconductors require multi-time programmable (MTP) intellectual property (IP) that does not require additional masks to trim analog circuits. In this paper, MTP cell size was reduced by about 18.4% by using MTP cells using PMOS capacitors (PCAPs) instead of NMOS capacitors (NCAPs) in MTP cells, which are single poly EEPROM cells with two transistors and one MOS capacitor for small-area MTP IP design. In addition, from the perspective of MTP IP circuit design, the two-stage voltage shifter circuit is applied to the CG drive circuit and TG drive circuit of MTP IP design, and in order to reduce the area of the DC-DC converter circuit, the VPP (=7.75V), VNN (=-7.75V) and VNNL (=-2.5V) charge pump circuits using the charge pumping method are placed separately for each charge pump.

• Journal of Advanced Marine Engineering and Technology
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• v.30 no.1
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• pp.125-133
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• 2006

It is important to understand flow characteristics and performances of sails for both sailors and designers who want to have efficient thrust of yacht In this Paper the viscous flows around sail-like rigid wings, which are similar to main and jib sails of a 30 feet sloop, are calculated using a CFD tool. Lift, drag and thrust forces are estimated for various conditions of gap distance between the two sails and the center of effort of the sail system is obtained. Wind tunnel experiments are also carried out to measure aerodynamic forces acting on the sails system and to validate the computation. It is found that the combination of two sails produces the lift force larger than the sum of that produced separately by each sail and the gap distance between the two sails is an important factor to determine total lift and thrust.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1503_1504
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• 2009

MEMS 구조물은 ${\mu}m$단위의 크기로 만들어지므로 각속도계와 같이 정밀한 센서를 만들 때에는 노이즈 문제를 해결하지 않으면 신호를 측정할 수가 없다. MEMS 구조물의 미세한 진동에 의해 발생되는 수 pico-coulomb의 전하를 측정해야하므로 구동 신호가 검출 전극에서 Feed-through되어 나타나는 경우 그 크기가 구동에 의한 신호보다 100배 이상 크기 때문에 원하는 신호를 검출할 수 없다. 본 논문에서는 이러한 Feed-through 현상에 의한 노이즈를 줄이기 위하여 Guard-ring을 이용한 blocking 방법과 dummy port를 이용한 canceling 방법을 고안하고 Feed-through reduction 회로를 설계, 제작, 실험하여 그 효과를 확인하였다. 그 결과 구동신호가 6Vpp, 30kHz일 때, -53.186dBm이었던 Feed-through 신호가 -77.107dBm으로 줄어드는 것을 확인하였다. 또한 노이즈를 제거하지 않은 경우 측정할 수 없었던 Q-factor를 Feed-through reduction 회로를 사용하여 측정한 결과 진공 패키징된 Si 기반 자이로스코프가 공진주파수 약 7.018kHz에서 Q-factor가 약 2500임을 확인하였다.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.3
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• pp.101-108
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• 2006

This paper describes the design, fabrication, and measured results of a W-band Cassegrain antenna suitable for the target detecting fuze sensor. The Cassegrain antenna is designed using MATLAB and MWS of CST. We use the multi-mode horn antenna as a feeder. The measurement results are as follows: The gain is about 41dB; SLL is 17.7dB; 3dB beamwidth is about $1.51^{\circ}$ in E-plane and $1.45^{\circ}$ in H-plane. The magnitude of leakage signals is about 43.5mVpp when the fabricated antenna and the transceiver of the fuze sensor ire combined. As a result, the designed W-band Cassegrain antenna could be quite applicable to the target detecting fuze sensor.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.133-136
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• 2002

This paper discusses the design of a sample-and -hold amplifier(SHA) that has a 12-bit resolution with a 100 MS/s speed. The sample-and-hold amplifier uses the open-loop architecture with hold-mode feedthrough cancellation for high accuracy and high sampling speed. The designed SHA is composed of input buffer, sampling switch, and output buffer with additional amplifier for offset cancellation Hard Ware. The input buffer is implemented with folded-cascode type operational transconductance Amplifier(OTA), and sampling switch is implemented with switched source follower(SSF). A spurious free dynamic range (SFDR) of this circuit is 72.6 dB al 100 MS/s. Input signal dynamic range is 1 Vpp differential. Power consumption is 65 ㎽.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.423-429
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• 2013

A 6-Gb/s differential voltage mode driver is presented whose output impedance and pre-emphasis level can be controlled independently. The voltage mode driver consists of five binary-weighted slices each of which has four sub-drivers. The output impedance is controlled by the number of enabled slices while the pre-emphasis level is determined by how many sub-drivers in the enabled slices are driven by post-cursor input. A prototype transmitter with a voltage-mode driver implemented in a 65-nm CMOS logic process consumes 34.8-mW from a 1.2-V power supply and its pre-emphasized output signal shows 165-mVpp,diff and 0.56-UI eye opening at the end of a cable with 10-dB loss at 3-GHz.

• Proceedings of the KIEE Conference
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• 2005.11a
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• pp.164-167
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• 2005

In this paper, the design and characteristics of a ${\pi}-shaped$ ultrasonic motor which is applicable to optical zoom operation of lenssystem for mobile phone are investigated. Its desi후 and simulation of performances are carried out by FEM (finite element method) commercial software. As a simulation result, by applying voltage with single phase, a combined vibration is produced at the surface of an arm of stator. The prototype of motor is fabricated and its outer size is 8*4*2 $mm^3$ including the cylindrical steel rod of 2 mm in diameter as rotor. The motor exhibits a maximum speed of 500 rpm and a power consumption of 0.3 W when driven at 20 Vpp and 64 kHz.