• Journal of the Korean Institute of Telematics and Electronics
• /
• v.24 no.4
• /
• pp.708-712
• /
• 1987

This paper deals with minimizing layout area of VLSI design. A long wire in a VLSI layout causes delay which can be reduced by using a driver. There can be significant area increase when many drivers are introduced in a layout. This paper describes a method to obtain tight bound on the worst-case increase in area when drivers are introduced along many long wires in a layout. The area occupied by minimum-area embedding for a circuit can depend on the aspect ratio of the bounding rectangle of the layout. This paper presents a separator-based area optimal embeddings for VLSI graphs in rectangles of several aspect ratios.

• Journal of the Institute of Convergence Signal Processing
• /
• v.4 no.4
• /
• pp.81-86
• /
• 2003

Current growth of VLSI design depends critically on the research and development of automatic layout tool. Automatic layout is composed of placement assigning a specific shape to a block and arranging the block on the layout surface and routing finding the interconnection of all the nets. Algorithms performing placement and routing impact on performance and area of VLSI design. Switchbox routing is a problem interconnecting each terminals on all four sides of the region, unlike channel routing. In this paper we propose a genetic algorithm searching solution space for switchbox routing problem. We compare the performance of proposed genetic algorithm(GA) for switchbox routing with that of other switchbox routing algorithm by analyzing the results of each implementation. Consequently experimental results show that out proposed algorithm reduce routing length and number of the via over the other switchbox routing algorithms.

• Journal of the Institute of Convergence Signal Processing
• /
• v.4 no.1
• /
• pp.64-70
• /
• 2003

Current growth of VLSI design depends critically on the research and development (If automatic layout tool. Automatic layout is composed of placement assigning a specific shape to a block and arranging the block on the layout surface and routing finding the interconnection of all the nets. Algorithms Performing placement and routing impact on Performance and area of VLSI design. Channel routing is a problem assigning each net to a track after global routing and minimizing the track that assigned each net. In this paper we propose a genetic algorithm searching solution space for the netlist partitioning problem for 4-layer channel routing. We compare the performance of proposed genetic algorithm(GA) for channel routing with that of simulated annealing(SA) algorithm by analyzing the results which are the solution of given problems. Consequently experimental results show that out proposed algorithm reduce area over the SA algorithm.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.1098-1100
• /
• 2005

The floorplanning problem is an essential design step in VLSI layout design and it is how to place rectangular modules as density as possible. And then, as the DSM advances, the VLSI chip becomes more congested even though more metal layers are used for routing. Usually, a VLSI chip includes several buses. As design increases in complexity, bus routing becomes a heavy task. To ease bus routing and avoid unnecessary iterations in physical design, we need to consider bus planning in early floorplanning stage. In this paper, we propose a floorplanning method for topological constraint consisting of bus constraint and memory constraint. The proposed algorithms based on Genetic Algorithm(GA) is adopted a sequence pair. For selection control, new objective functions are introduced for topological constraint. Studies on floor planning and cell placement have been reported as being applications of GA to the LSI layout problem. However, no studies have ever seen the effect of applying GA in consideration of topological constraint. Experimental results show improvement of bus and memory constraint.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.3
• /
• pp.124-130
• /
• 1990

This paper presents a new layout language, HAN-LALA (HANyang LAyout LAnguage), to automate the LSI/VLSI layout design. HAN-LALA is a C extension, which is easy to describe the layout. As HAN-LALA is directly compiled with no preprocessor, it renders easy debugging and short design time. For the technology independent layout design, the design rules and the process technologies are organized into seperate modules. The related objects are grouped and the placement is performed on the groups. Also the various routing modules including a river routing module and the one which can consider the forbidden regions make the layout design error-free without detailed descriptions of the layout.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.29A no.1
• /
• pp.48-59
• /
• 1992

This paper presents the design of a layout processing system that performs circuit and symbolic extraction from hierarchical designs containing arbitrarily shaped layout. The system is flexible enough to deal with various technologies, MOS or bipolar, by providing extraction rules in the form of technology files. In this paper, new efficient algorithms for trapezoidal decomposition of polygon and symbolic path extraction using trapezoidal template are proposed for symbolic extraction. Circuit and symbolic extractor is developed as an integrated design environment of SOLID system.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.28A no.1
• /
• pp.60-73
• /
• 1991

This paper presents an efficient algorithm for incremental and hierarchical design rule checking of VLSI layouts, and describes the implementation of a layout editor using the proposed algorithm. Tracing the sliced edges divided by the intersection of the edges either ina polygon or in two polygons (Sliced-Edge Trace), the algorithm performs VLSI pattern operations like resizing and other Boolean operations. The algorithm is not only fast enough to check the layouts of full-custom designs in real-time, but is general enough to be used for arbitrarily shaped polygons. The proposed algorithm was employed in developingt a layout editor on engineering workstations running UNIX. The editor has been successfully used for checking, generating and resizing of VLSI layouts.

• ETRI Journal
• /
• v.7 no.3
• /
• pp.3-11
• /
• 1985

CAD tools that has the common data base system are important to design for the VLSI. Each CAD tools are used to design for the VLSI, and to reduce the complexity, man-error, design-time for the IC design. CIF, a layout description language, was proved to be effective in this point. In this article, the program which translates pattern generation data for the mask tooling into CIF data was described. This program has its character in the unification of physical design data base for a design automated CAD system. The output format of CIF data is fitting to the input of the kgraph that is graphic layout editor, and the name of each layer and the output file is extended as a user's option.

• Proceedings of the KIEE Conference
• /
• 1988.07a
• /
• pp.582-586
• /
• 1988

This paper describes KUIC_DRC(Kyungpook national University Intelligent CAD_Design Rule Checker) which verifies VLSI layout. It uses modified linked list data structure. The input form is modifed CIF(Caltech Intermediate Form), called KIF(Kyungpook Intermediate Form). It makes error file, a KIF file. It is written in C language and excuted on MS-DOS, in IBM PC/AT.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.24 no.5
• /
• pp.887-895
• /
• 1987

This paper deals with the CMOS PLA Generator using CHISEL language. The program which plots a CMOS PLA alphanumeric layout automatically according to desired input functions and output functions has been developed. The program consists of procedures. These procedure are drawing a stick diagram with input data, converting any design rule, plotting a physical layout at IBM PC-AT with CIF input data. Physical layout information of dynamic CMOS PLA is stored CIF form. The CMOS PLA Generator is written in CHISEL which is layout language VLSI design tools and run on a VAX11/750 running UNIX.