A Hierarchical and Incremental DRC System Using Sliced-Edge Trace Algorithm

Sliced-Edge Trace 알고리듬을 이용한 계층적 Incremental DRC 시스템

This paper presents an efficient algorithm for incremental and hierarchical design rule checking of VLSI layouts, and describes the implementation of a layout editor using the proposed algorithm. Tracing the sliced edges divided by the intersection of the edges either ina polygon or in two polygons (Sliced-Edge Trace), the algorithm performs VLSI pattern operations like resizing and other Boolean operations. The algorithm is not only fast enough to check the layouts of full-custom designs in real-time, but is general enough to be used for arbitrarily shaped polygons. The proposed algorithm was employed in developingt a layout editor on engineering workstations running UNIX. The editor has been successfully used for checking, generating and resizing of VLSI layouts.