• Nuclear Engineering and Technology
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• v.53 no.4
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• pp.1167-1175
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• 2021

The process of automation and monitoring in industrial control system involves the use of many types of sensors. A programmable logic controller plays an important role in the automation of the different processes in the power plant system. The major control units are boiler for temperature and pressure, turbine for speed of motor, generator for voltage, conveyer belt for fuel. The power plant units are controlled using microcontrollers and PLCs, but FPGA can be the feasible solution. The paper focused on the design and simulation of hardware chip to monitor boiler, turbine, generator and conveyer belt. The hardware chip of the plant is designed in Xilinx Vivado Simulator 17.4 software using VHDL programming. The methodology includes VHDL code design, simulation, verification and testing on Virtex-5 FPGA hardware. The system has four independent buzzers used to indicate the status of the boiler, generator, turbine motor and conveyer belt in on/off conditions respectively. The GSM is used to display corresponding message on the mobile to know the status of the device in on/off condition. The system is very much helpful for the industries working on plant automation with FPGA hardware integration.

• Proceedings of the KAIS Fall Conference
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• 2002.11a
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• pp.159-162
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• 2002

본 논문에서는 대역확산 방식으로 제안되고 있는 CDMA 시스템의 송수신 모뎀을 FPGA를 이용하여 설계 및 검증을 수행하였다. 송신기에서는 Walsh code(N=16), PN(7 stage=127chip)code를 데이터에 곱하여서 송신하고, 수신기에서는 송신기에서 사용했던 Walsh code(N=16)와 PN code를 사용하여 역확산 후 source data를 확인하였다. 송수신기의 설계는 Xilinx사의 FPGA 디자인 툴인 Xilinx foundation3.1을 사용하여 VHDL simulation을 수행하였고, FPGA 회로설계 검증 장비인 EDA-Lab 3000 장비를 사용하여 Xilinx사의 SPARTAN2 2S100PQ208칩에 다운로드 한 후 에뮬레이션 툴 인 Design-Pro shop을 사용하여 설계된 회로의 동작을 확인하였다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.20-28
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• 1997

In this paper, quantization and inverse quantizatio unit, a sa component of MPEG-2 moving picture compression system, ar edesigned. In the processing of quantization, this design adopted newly designed arithmetic units in which quantization matrices and scale code was expressed with SD(signed-digit) code. In the arithmetic unit of inverse quantization, quantization scale code, which has 5-bits length, is splited into two pieces; 2-bits for control code, 3-bits for quantization data, and the method to devise quantization step size is proposed. The design was coded with VHDL and synthesis results in that it consumed about 6,110 gates, and operating speed is 52MHz.

• The KIPS Transactions:PartC
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• v.10C no.2
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• pp.233-240
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• 2003

In this paper, an improved architecture of turbo codec for IMT-2000 is proposed. The encoder consists of an interleaver using an on-the-fly type address generator and a modified shift register instead of an external RAM, and the decoder uses a decreased number of RAM. The proposed architecture is simulated with C/VHDL languages, where BER (bit-error-rate) performances are generally in agreement with previous data by varying interaction numbers, interleaver block sizes and code rates.

• The Journal of the Acoustical Society of Korea
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• v.18 no.1
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• pp.45-52
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• 1999

In this thesis, a packer is proposed and designed for removing the bottle-neck effect and easy signal processing using a new algorithm with the operation frequency of 54MHz. To verify the performance of the proposed packer, DCT coefficient encoding block with ROM table using a combinational logic is designed and its output data are used the input data of the packer. Circuits in this thesis are designed by using VHDL code and its modeling and simulation are performed by SYNOPSYS tool using $0.65{\mu}m$ rule.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.438-441
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• 2000

In this paper, Turbo rode is describing a performance near the Shannon's channel capacity limit. So, basic theory of turbo code and MAP,Log-MAP decoding algorithm was arranged. The foundation of this using VHDL, Log-MAP turbodecoder was implemented by Altera´s FLEX10K CPLD.

• The Journal of Information Technology
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• v.3 no.1
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• pp.29-36
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• 2000

Viterbi decoder is a maximum likelihood decoding method for convolution coding used in satellite and mobile communications. In this paper, a Viterbi decoder with constraint length of K=7, 3 bit soft decision and traceback depth of ${\Gamma}=96$ for convolution code is implemented using VHDL. The hardware size of designed decoder is reduced by 4 bit pre-traceback in the survivor memory.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.1-7
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• 1997

In tis paper, w eproposed a modeling for direct-sequence spread communication base band modem in RT-level VHDL and implemented in a one-chip VLSI and tested. The transmitter modulates with DQPSK modulation method and spreads a modulated signal with 32-bit PN code into 1.152MHz. The receiver de-spreads a signal using 32-tap matched filter and recovers with DQPSK demodulation method. The digital frequency synthesizer generates the sine signal and the cosine signal of 2.304MHz with ROM tables in the size of 7$\^$*/256 and 6$\^$*/256, respectively. The implemented VLSI has been verified a BER with 10$\^$-4/ at E$\_$b//N$\_$o/ of 13dB with a SPW fixed design model and fabricated in the 0.8.mu.m KG6423 gate array with a VHDL model.

• The KIPS Transactions:PartC
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• v.8C no.1
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• pp.32-40
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• 2001

In this paper, we propose a high-speed modular multiplication algorithm which revises conventional Montgomery's algorithm. A hardware architecture is also presented to implement 1024-bit RSA cryptosystem for digital signature based on the proposed algorithm. Each iteration in our approach requires only one addition operation for two n-bit integers, while that in Montgomery's requires two addition operations for three n-bit integers. The system which is modelled in VHDL(VHSIC Hardware Description Language) is simulated in functionally through the use of $Synopsys^{TM}$ tools on a Axil-320 workstation, where Altera 10K libraries are used for logic synthesis. For FPGA implementation, timing simulation is also performed through the use of Altera MAX + PLUS II. Experimental results show that the proposed RSA cryptosystem has distinctive features that not only computation speed is faster but also hardware area is drastically reduced compared to conventional approach.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7B
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• pp.1393-1399
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• 1999

In this paper, a VLSI design of the convolutional codec chip of code rate r=l/3, and constraint length K=9 is presented, which is able to correct errors of the received data when transmitted data is corrupted in channels. The circuit design mainly aimed for simple implementation. In the decoder, Viterbi algorithm with 3-bit soft-decision is employed. For information sequence updating and storage, the register exchange method is employed, where the register length is 5$\times$K(45 stages). The codec chip is designed using VHDL language and Design Analyzer and VHDL Simulator of Synopsys are used for simulation and synthesis. The chip is composed of ENCODER block, ALIGN block, BMC block, ACS block, SEL_MIN block and REG_EXCH block. The operation of the codec chip is verified though the logic simulations, where several error conditions are assumed. As a result of the timing simulation after synthesis, the decoding speed of 325.5Kbps is achieved, and 6,894 gates is used.