• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.236.2-236.2
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• 2014

세계 반도체 시장은 컴퓨터 기능이 더해진 모바일 기기의 수요가 증가함에 따라 메모리반도체의 시장규모가 최근 빠른 속도로 증가했다. 특히 모바일 기기에서 저장장치 역할을 하는 비휘발성 반도체인 NAND Flash Memory는 스마트폰 및 태블릿PC 등 휴대용 기기의 수요 증가, SSD (Solid State Drive)를 탑재한 PC의 수요 확대, 서버용 SSD시장의 활성화 등으로 연평균 18.9%의 성장을 보이고 있다. 이러한 경제적인 배경 속에서 NAND Flash 미세공정 기술의 마지막 단계로 여겨지는 1Xnm 공정이 개발되었다. 그러나 1Xnm Flash Memory의 생산은 새로운 제조설비 구축과 차세대 공정 기술의 적용으로 제조비용이 상승하는 단점이 있다. 이에 따라 제조공정기술을 미세화하지 않고 기존의 수평적 셀구조에서 수직적 셀구조로 설계 구조를 다양화하는 기술이 대두되고 있는데 이 중 Flash Memory의 대용량화와 수명 향상을 동시에 추구할 수 있는 3D NAND 기술이 주목을 받게 되면서 공정기술의 변화도 함께 대두되고 있다. 3D NAND 기술은 기존라인에서 전환하는데 드는 비용이 크지 않으며, 노광장비의 중요도가 축소되는 반면, 증착(Chemical Vapor Deposition) 및 식각공정(Etching)의 기술적 난이도와 스텝수가 증가한다. 이 중 V-NAND 3D 기술에서 사용하는 박막증착 공정의 경우 산화막과 질화막을 번갈아 증착하여 30layer 이상을 하나의 챔버 내에서 연속으로 증착한다. 다층막 증착 공정이 비정상적으로 진행되었을 경우, V-NAND Flash Memory를 제조하기 위한 후속공정에 영향을 미쳐 웨이퍼를 폐기해야 하는 손실을 초래할 수 있다. 본 연구에서는 V-NAND 다층막 증착공정 중에 다층막의 두께를 가상 계측하는 알고리즘을 개발하고자 하였다. 증착공정이 진행될수록 박막의 두께는 증가하여 커패시터 관점에서 변화가 생겨 RF 신호의 진폭과 위상의 변화가 생긴다는 점을 착안하여 증착 공정 중 PECVD 장비 RF matcher와 heater에서 RF 신호의 진폭과 위상을 실시간으로 측정하여 데이터를 수집하고, 박막의 두께와의 상관성을 분석하였다. 이 연구 결과를 토대로 V-NAND Flash memory 제조 품질향상 및 웨이퍼 손실 최소화를 실현하여 제조 시스템을 효율적으로 운영할 수 있는 효과를 기대할 수 있다.

• Journal of IKEEE
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• v.28 no.1
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• pp.110-115
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• 2024

This paper analyzed the V_th (Threshold Voltage) variations in 3D NAND Flash memory with tapered O/N/O (Oxide/Nitride/Oxide) structure and O/N/F (Oxide/Nitride/Ferroelectric) structure, where the blocking oxide is replaced by ferroelectric material. With a tapering angle of 0°, the O/N/F structure exhibits lower resistance compared to the O/N/O structure, resulting in reduced V_th variations in both the upper and lower regions of the WL (Word Line). Tapered 3D NAND Flash memory shows a decrease in channel area and an increase in channel resistance as it moves from the upper to the lower WL. Consequently, as the tapering angle increases, the V_th decreases in the upper WL and increases in the lower WL. The tapered O/N/F structure, influenced by V_fe proportional to the channel radius, leads to a greater reduction in V_th in the upper WL compared to the O/N/O structure. Additionally, the lower WL in the O/N/F structure experiences a greater increase in V_th compared to the O/N/O structure, resulting in larger V_th variations with increasing tapering angles.

• Journal of IKEEE
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• v.26 no.2
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• pp.329-332
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• 2022

In this paper, retention characteristics of lateral charge migration according to parameters of 3D NAND flash memory to which ferroelectric (HfO₂) structure is applied and ∆V_th were analyzed. The larger the P_s, the greater maximum polarization possible in ferroelectric during Programming. Therefore, the initial V_th increases by about 1.04V difference at P_s 70µC/cm² than at P_s 25µC/cm². Also, electrons trapped after the Program operation causes lateral charge migration over time. Since ferroelectric maintains polarization without applying voltage to the gate after Programming, regardless of P_s value, polarization increases as P_r increases and the ∆V_th due to lateral charge migration becomes smaller by about 1.54V difference at P_r 50µC/cm² than P_r 5µC/cm².

• Journal of IKEEE
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• v.25 no.4
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• pp.770-773
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• 2021

In this paper, the retention characteristics of 3D NAND flash memory applied with tapering and ferroelectric (HfO₂) structure were analyzed after programming operation. Electrons trapped in nitride are affected by lateral charge migration over time. It was confirmed that more lateral charge migration occurred in the channel thickened by tapering of the trapped electrons. In addition, the Oxide-Nitride-Ferroelectric (ONF) structure has better lateral charge migration due to polarization, so the change in threshold voltage (V_th) is reduced compared to the Oxide-Nitride-Oxide (ONO) structure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.566-571
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• 2014

Channel-stacked 3D NAND flash memory is very promising candidate for the next-generation NAND flash memory. However, there is an inherent issue on cell size variation between stacked channels due to the declined etch slope. In this paper, the effect of the cell variation on the incremental step pulse programming (ISPP) characteristics is studied with 3D TCAD simulation. The ISPP slope degradation of elliptical channel is investigated. To solve that problem, a new programming method is proposed, and we can alleviate the $V_T$ variation among cells and reduce the total programming time.

• Proceedings of the Korean Society of Computer Information Conference
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• 2014.07a
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• pp.227-229
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• 2014

플래시 메모리는 빠른 처리 속도, 비휘발성, 저 전력, 강한 내구성 등으로 인해 최근 스마트폰, 태블릿, 노트북, 컴퓨터와 같은 여러 분야에서 많이 사용하고 있다. 최근 기존에 사용하던 NAND 플래시가 미세화 기술의 한계에 봉착함에 따라 기존 2차원 구조의 NAND플래시를 대처할 장치로 3차원 수직구조 NAND 플래시 메모리(3D Vertical NAND)가 주목받고 있다. 기존의 플래시 메모리는 데이터를 효율적으로 삽입/삭제/검색하기 위해 B-tree와 같은 색인기법을 필요로 한다. 플래시 메모리 상에서 B-tree 구현에 관한 기존 연구로서는 BFTL(B-Tree Flash Translation Layer)기법이 최초로 제안되었다. 현재 3차원 V-NAND 구조의 플래시 메모리가 시작품으로 제작되어 머지않아 양산 될 예정이다. 본 논문에서는 향후 출시될 3차원 구조의 플래시 메모리에 적합한 Octree 기반의 파일시스템을 제안한다.

• Journal of IKEEE
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• v.27 no.4
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• pp.399-404
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• 2023

In this paper, we analyzed the current path in the O/N/O (Oxide/Nitride/Oxide) structure of 3D NAND Flash memory and in the O/N/F (Oxide/Nitride/Ferroelectric) structure where the blocking oxide is replaced by a ferroelectric. In the O/N/O structure, when V_read is applied, a current path is formed on the backside of the channel due to the E-fields of neighboring cells. In contrast, the O/N/F structure exhibits a current path formed on the front side due to the polarization of the ferroelectric material, causing electrons to move toward the channel front. Additionally, we performed an examination of device characteristics considering channel thickness and channel length. The analysis results showed that the front electron current density in the O/N/F structure increased by 2.8 times compared to the O/N/O structure, and the front electron current density ratio of the O/N/F structure was 17.7% higher. Therefore, the front current path is formed more effectively in the O/N/F structure than in the O/N/O structure.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.1
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• pp.1-7
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• 2000

The SNOSFET memory devices with ultrathin ONO(tunnel oxide-nitride-blocking oxide) gate dielectric were fabricated using n-well CMOS process and investigated its characteristics. The thicknesses of tunnel oxide, nitride and blocking oxide were $23{\AA},\; 53{\AA}\; and\; 33{\AA}$, respectively. Auger analysis shows that the ONO layer is made up of $SiO_2(upper layer of blocking oxide)/O-rich\; SiO_x\N\_y$. It clearly shows that the converting layer with $SiO_x\N\_y(lower layer of blocking oxide)/N-rich SiO_x\N\_y(nitride)/O-rich SiO_x\N\_y(tunnel oxide)$. It clearly shows that the converting layer with $SiO_x\N\_y$ phase exists near the interface between the blocking oxide and nitride. The programming condition of +8 V, 20 ms, -8 V, 50 ms is determined and data retention over 10 years is obtained. Under the condition of 8 V programming, it was confirmed that the modified Fowler-Nordheim tunneling id dominant charge transport mechanism. The programmed threshold voltage is distributed less than 0.1 V so that the reading error of memory stated can be minimized. An $8\times8$ NAND type flash EEPROM with SONOSFET memory cell was designed and simulated with the extracted SPICE parameters. The sufficient read cell current was obtained and the upper limit of $V_{TH}$ for write state was over 2V.

• Journal of the Semiconductor & Display Technology
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• v.18 no.2
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• pp.82-86
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• 2019

The reliability of 3D NAND flash memory cell is affected by the charge migration which can be divided into the vertical migration and the lateral migration. To clarify the difference of two migrations, the activation energy of the charge loss is extracted and compared in a conventional square device pattern and a new test pattern where the perimeter of the gate is exaggerated but the area is same. The charge loss is larger in the suggested test pattern and the activation energy is extracted to be 0.058 eV while the activation energy is 0.28 eV in the square pattern.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.2
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• pp.125-131
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• 2001

When the program voltage is applied to a word line, a part of the boosted channel charge in inhibited bit lines is lost due to the coupling between the string select line (SSL) and the adjacent word line. This phenomenon causes the program disturbance in the cells connected to the inhibited bit lines. This program disturbance becomes more serious, as the word line pitch is decreased. To reduce the word line coupling, the rising edge of the word-line voltage waveform was changed from a pulse step into a ramp waveform with a controlled slope. The word-line ramping circuit was composed of a timer, a decoder, a 8 b D/A converter, a comparator, and a high voltage switch pump (HVSP). The ramping voltage was generated by using a stepping waveform. The rising time and the stepping number of the word-line voltage for programming were set to $\mutextrm{m}-$ and 8, respectively,. The ramping circuit was used in a 512Mb NAND flash memory fabricated with a $0.15-\mutextrm{m}$ CMOS technology, reducing the SSL coupling voltage from 1.4V into a value below 0.4V.