• Title/Summary/Keyword: V-128

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Clinical Reports of the Meniere's Disease in the Diagnosis of Deficiency-Excess (메니에르 병 환자의 허실별(虛實別) 치험례)

  • Jang, Soo-Young;Shin, Hyeon-Cheol
    • The Journal of Internal Korean Medicine
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    • v.32 no.1
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    • pp.121-128
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    • 2011
  • Meniere's disease is an idiopathic syndrome of endolymphatic hydrops characterized by episodic vertigo, tinnitus, fluctuating hearing loss and ear fullness. The etiology and pathophysiology of the disease is still disputed. As yet, no treatment has conclusively modified the clinical course of the condition and thereby prevented the associated progressive hearing loss. We observed two cases of Meniere's disease treated with oriental herbal medication by the diagnosis of Deficiency-Excess. One patient had taken BangHyunOnDam-tang, and the other had taken ChungGanESa-tang. After treatment, vertigo attacks were controlled in both. Tinnitus and hearing loss were improved in one patient and unchanged in the other. Therefore, we believe that oriental herbal treatment may be a therapeutic modality that is effective in controlling Meniere's disease.

Age Studies on the Butter Fish Population from Southwestern Waters of Korea

  • Han, Pyung Chin
    • 한국해양학회지
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    • v.8 no.2
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    • pp.68-74
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    • 1973
  • The present paper concerns the age determination and growth of butter fish, Pampus argenteus from the southwestern waters of Korea by otolith reading. 743 specimens taken by stow-net in the southern part of the Yellow Sea and northeastern part of the East China Sea during the period from October 1972 to September 1973 were examined. Results of the study are summarized as follows: 1. Sex ratio of females to males was found to be 2:1. 2. Ring marks on the otolith were found to be formed twice a year, once during the period of January-May and the other time in September. 3. The Lee's phenomenon was observed on the otolith sample. 4. The relationship between the radius of otolith(R) and fork length(L) was found to be as follows: R=0.3069+0.0133L 5. Calculated fork length at the time of otolith ring formation are found to be as follows:I-ring,71.67mm; II-ring, 125.05mm; III-ring, 168.65mm; IV-ring, 201.74mm; V-ring, 225.80mm; VI-ring, 240.84mm. 6. Maximum fork length calculated according to the diagram of Walford's growth transformation was found to be 281.5mm. 7. Growth curve, when related to the von Bertalanffy's equation, was laid out as $L_{t}=281.5[1-e$^{-0.674(t-0.128)}]$

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Development of PC-based Auto Inspection System for Smart Battery Protection Circuit Module (PC기반의 스마트 배터리 보호모듈 자동 검사 시스템 개발)

  • Yoon, Tae-Sung;Jang, Gi-Won;Park, Ju-No;Lee, Jeong-Jae
    • Proceedings of the KIEE Conference
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    • 2005.05a
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    • pp.275-277
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    • 2005
  • In a lithium-ion battery which is being used in many portable electronic goods, electrolyte is disaggregated and then the gas is happened when electric charging volt is over the 4.5V. So, the pressure on the safety valve is increased and electrolyte is leaked out in the cell. It leads to the risk of explosion. On the other hand, in the case which the battery is discharged excessively, the negative pole is damaged and the performance of the battery is deteriorated. The protection module of a lithium-ion battery is used for preventing such risk and the inspection system is needed to check the performance of such protection module. In this research, a PC-based auto inspection system is developed for the inspection of a battery protection module using Dallas chipset. In the inspection system, AVRl28 chip is used as a controller and the communication protocol is developed for the data communication between the protection module and the AVR128 chip. And GPIB interface is used for the control of measuring devices. Also, MMI environment is developed using LabView for convenient monitoring by the tester.

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Improvement of Thermoelectric Properties of Bismuth Telluride Thin Films using Rapid Thermal Processing (Bismuth Telluride 박막의 열전특성 개선을 위한 급속 열처리효과)

  • Kim, Dong-Ho;Lee, Gun-Hwan
    • Korean Journal of Materials Research
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    • v.16 no.5
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    • pp.292-296
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    • 2006
  • Effects of rapid thermal annealing of bismuth telluride thin films on their thermoelectric properties were investigated. Films with four different compositions were elaborated by co-sputtering of Bi and Te targets. Rapid thermal treatments in range of $300{\sim}400^{\circ}C$ were carried out during 10 minutes under the reducing atmosphere (Ar with 10% $H_2$). As the temperature of thermal treatment increased, carrier concentrations of films decreased while their mobilities increased. These changes were clearly observed for the films close to the stoichiometric composition. Rapid thermal treatment was found to be effective in improving the thermoelectric properties of $Bi_2Te_3$ films. Recrystallization of $Bi_2Te_3$ phase has caused the enhancement of thermoelectric properties, along with the decrease of the carrier concentration. Maximum values of Seebeck coefficient and power factor were obtained for the films treated at $400^{\circ}C$ (about $-128{\mu}V/K$ and $9{\times}10^{-4}\;W/K^2m$, respectively). With further higher temperature ($500^{\circ}C$), thermoelectric properties deteriorated due to the evaporation of Te element and subsequent disruption of film's structure.

Design and implementation of the SliM image processor chip (SliM 이미지 프로세서 칩 설계 및 구현)

  • 옹수환;선우명훈
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.10
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    • pp.186-194
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    • 1996
  • The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

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Annealing Effects of Tunneling Dielectrics Stacked $SiO_2/Si_3N_4$ Layers for Non-volatile Memory (비휘발성 메모리를 위한 $SiO_2/Si_3N_4$ 적층 구조를 갖는 터널링 절연막의 열처리 효과)

  • Kim, Min-Soo;Jung, Myung-Ho;Kim, Kwan-Su;Park, Goon-Ho;Jung, Jong-Wan;Chung, Hong-Bay;Cho, Won-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.128-129
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    • 2008
  • The annealing effects of $SiO_2/Si_3N_4$ stacked tunneling dielectrics were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_3N_4/SiO_2/Si_3N_4$(NON), $SiO_2/Si_3N_4/SiO_2$(ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS(Metal-Oxide-Semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field and improved electrical characteristics by annealing processes than $SiO_2$ layer.

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A 2.4GHz Back-gate Tuned VCO with Digital/Analog Tuning Inputs (디지털/아날로그 입력을 통한 백게이트 튜닝 2.4 GHz VCO 설계)

  • Oh, Beom-Seok;Lee, Dae-Hee;Jung, Wung
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2003.11a
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    • pp.234-238
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    • 2003
  • In this work, we have designed a fully integrated 2.4GHz LC-tuned voltage-controlled oscillator (VCO) with multiple tuning inputs for a $0.25-{\mu}m$ standard CMOS Process. The design of voltage-controlled oscillator is based on an LC-resonator with a spiral inductor of octagonal type and pMOS-varactors. Only two metal layer have been used in the designed inductor. The frequency tuning is achieved by using parallel pMOS transistors as varactors and back-gate tuned pMOS transistors in an active region. Coarse tuning is achieved by using 3-bit pMOS-varactors and fine tuning is performed by using back-gate tuned pMOS transistors in the active region. When 3-bit digital and analog inputs are applied to the designed circuits, voltage-controlled oscillator shows the tuning feature of frequency range between 2.3 GHz and 2.64 GHz. At the power supply voltage of 2.5 V, phase noise is -128dBc/Hz at 3MHz offset from the carrier, Total power dissipation is 7.5 mW.

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Simulation and Model Validation of a Pneumatic Conveying Drying for Wood Dust Particles

  • Bhattarai, Sujala;Kim, Dae-Hyun;Oh, Jae-Heun
    • Journal of Biosystems Engineering
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    • v.37 no.2
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    • pp.82-89
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    • 2012
  • Purpose: The simulation model of a pneumatic conveying drying (PCD) for sawdust was developed and verified with the experiments. Method: The thermal behavior and mass transfer of a PCD were modeled and investigated by comparing the experimental results given by a reference (Kamei et al. 1952) to validate the model. Momentum, energy and mass balance, one dimensional first order ordinary differential equations, were coded and solved into Matlab V. 7.1.0 (2009). Results: The simulation results showed that the moisture content reduced from 194% to 40% (dry basis), air temperature decreased from $512^{\circ}C$ to $128^{\circ}C$ with the particle residence time of 0.7 seconds. The statistical indicators, root mean square error and R-squared, were calculated to be 0.079, and 0.998, respectively, between the measured and predicted values of moisture content. The relative error between the measured and predicted values of the final pressured drop, air temperature, and air velocity were only 8.96%, 0.39% and 1.05% respectively. Conclusions: The predicted moisture content, final temperature, and pressure drop values were in good agreement with the experimental results. The developed model can be used for design and estimation of PCD system for drying of wood dust particles.

The Study for Selection of the Optimum Route by Economic Analyses (설계의 경제성 분석을 통한 최적노선 선정방안 연구 - OO경전철 민간투자사업 사례연구 -)

  • Kwon, Suk-Hyun;Seo, Sung-Han;Lee, Dong-Woo
    • Proceedings of the KSR Conference
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    • 2008.06a
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    • pp.128-138
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    • 2008
  • VE of the scripture season enterprises and it respected LCC analyzes from the research which it sees and to use AHP techniques and definite LCC techniques and probabilistic LCC techniques selects the optimum route the case study which it executed. It presented the quality rating model in about the resultant most route lascivious at the time of VE evaluation, in order to select the alternative of optimum AHP techniques which are one in decision-making technique and an evaluation item by weight and a grade it applied the mountaintop it did. Also the definite LCC analyzer law departments of existing together it applied the probabilistic LCC techniques which use Monte Carlo Simulation in about analytical prices and reliability height boil. The economical efficiency was excellent with VE/LCC analytical resultant route and facility size abridgment, the rivers most it will be able to minimize an environmental effect with short distance traverse, the selection this hit preparation LCC which separates from the land use side decreased, the value (V) above 22.0% with the fact that it improves. And, the reliability of the probabilistic LCC analytical resultant analytical results in compliance with Monte Carlo Simulation with 90.3% was very analyzed with the fact that it is a high level.

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An Amorphous Silicon Local Interconnection (ASLI) CMOS with Self-Aligned Source/Drain and Its Electrical Characteristics

  • Yoon, Yong-Sun;Baek, Kyu-Ha;Park, Jong-Moon;Nam, Kee-Soo
    • ETRI Journal
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    • v.19 no.4
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    • pp.402-413
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    • 1997
  • A CMOS device which has an extended heavily-doped amorphous silicon source/drain layer on the field oxide and an amorphous silicon local interconnection (ASLI) layer in the self-aligned source/drain region has been studied. The ASLI layer has some important roles of the local interconnections from the extended source/drain to the bulk source/drain and the path of the dopant diffusion sources to the bulk. The junction depth and the area of the source/drain can be controlled easily by the ASLI layer thickness. The device in this paper not only has very small area of source/drain junctions, but has very shallow junction depths than those of the conventional CMOS device. An operating speed, however, is enhanced significantly compared with the conventional ones, because the junction capacitance of the source/drain is reduced remarkably due to the very small area of source/drain junctions. For a 71-stage unloaded CMOS ring oscillator, 128 ps/gate has been obtained at power supply voltage of 3.3V. Utilizing this proposed structure, a buried channel PMOS device for the deep submicron regime, known to be difficult to implement, can be fabricated easily.

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