• Journal of Astronomy and Space Sciences
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• v.23 no.3
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• pp.245-258
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• 2006

In this paper, an automation algorithm of analyzing and scheduling the station-keeping maneuver is presented for Communication, Ocean and Meteorological Satellite (COMS). The perturbation analysis for keeping the position of the geostationary satellite is performed by analytic methods. The east/west and north/south station-keeping maneuvers we simulated for COMS. Weekly east/west and biweekly north/south station-keeping maneuvers are investigated for a period of one year. Various station-keeping orbital parameters are analyzed. As the position of COMS is not yet decided at either $128.2^{\circ}E\;or\;116.0^{\circ}E$, both cases are simulated. For the case of $128.2^{\circ}E$, east/west station-keeping requires ${\Delta}V$ of 3.50m/s and north/south station-keeping requires ${\Delta}V$ of 52.71m/s for the year 2009. For the case of $116.0^{\circ}E,\;{\Delta}V$ of 3.86m/s and ${\Delta}V$ of 52.71m/s are required for east/west and north/south station-keeping, respectively. The results show that the station-keeping maneuver of COMS is more effective at $128.2^{\circ}E$.

• ETRI Journal
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• v.32 no.1
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• pp.1-10
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• 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.67-74
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• 2004

In this paper, a 3.3V 8-bit 500MSPS based on an interpolation architecture CMOS A/D converter is designed. In order to overcome the problems of high speed operation, a novel pre-amplifier, a circuit for the Reference Fluctuation, and an Averaging Resistor are proposed. The proposed Interpolation A/D Converter consists of Track ＆ Hold, four resistive ladders with 256 taps, 128 comparators, and digital blocks. The proposed A/D Converter is based on 0.35um 2-poly 4-metal N-well CMOS technology. The A/D Converter dissipates 440 mW at a 3.3 Volt single power supply and occupies a chip area of 2250um x 3080um.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.3
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• pp.427-433
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• 2002

This paper describes a design of cryptographic processor that implements the AES(Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation, the round block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.-V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.7
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• pp.1332-1340
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• 2007

This paper describes an efficient hardware design of key wrap/unwrap algorithm for security layer of WiBro system. The key wrap/unwrap core (WB_KeyWuW) is based on AES (Advanced Encryption Standard) algorithm, and performs encryption/decryption of 128bit TEK (Traffic Encryption Key) with 128bit KEK (Key Encryption Key). In order to achieve m area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented by using field transformation technique. As a result, the gate count of the WB_KeyWuW core is reduced by about 25% compared with conventional LUT (Lookup Table)-based design. The WB_KeyWuW con designed in Verilog-HDL has about 14,300 gates, and the estimated throughput is about $16{\sim}22-Mbps$ at 100-MHz@3.3V, thus the designed core can be used as an IP for the hardware design of WiBro security system.

• Journal of IKEEE
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• v.18 no.1
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• pp.128-133
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• 2014

This paper suggest hysteretic buck converter using thermistor that can improve output ripple voltage according to temperature to improve. In case of high temperature where circuit is sensitive, it decides two comparable voltages high. And, in case of non-high temperature where circuit is stable, it decides two comparable voltages low, then it minimizes output ripple voltage. simulation result what is included in this paper describe that output ripple voltage is reduced more than 30mV by using suggested converter, and load regulation was 0.011mV/mA. Suggested circuit is suitable to power managing circuit that operate digital circuit requiring fast response and low power.

• Journal of fish pathology
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• v.35 no.1
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• pp.121-128
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• 2022

Recent studies revealed that histone proteins are involved in innate immune responses during pathogen invasion as well as DNA packing. This study characterized the histone genes (H2A.V) of sevenband groupers and analyzed gene expression in NNV-infected sevenband groupers. The open reading frame (ORF) of H2A.V is 387 bp which encoded 128 amino acid residues. The deduced amino acid sequence of H2A.V harbor a highly conserved domain for H2A/H2B/H3 and H2A_C binding domain. Quantitative real-time PCR analysis showed that H2A.V had a high gene expression level in the brain and blood after being NNV-infected. An increase in extracellular histone protein in the blood has been identified as a biomarker for vascular function in humans. More research is required to understand histone's immune response at the protein level or in aquatic animals.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04a
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• pp.363-366
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• 2001

LILI-128 스트림 암호는 IMT-2000 무선단말간 데이터 암호화를 위하여 제안된 128-비트 크기의 스트림 암호방식이며, 클럭 조절형태의 채택에 따라 속도저하라는 구조적인 문제점을 안고 있다. 본 논문에서는 귀환/이동에 있어서 랜덤한 4개의 연결 경로를 갖는 4-비트병렬 $LFSR_{d}$를 제안함으로서 속도문제를 해결하였다. 그리고 ALTERA 사의 FPGA 소자(EPF10K20RC240-3)를 선정하여 그래픽/VHDL 하드웨어 구현 및 타이밍 시뮬레이션을 실시하였으며, 50MHz 시스템 클럭에서 안정적인 50Mbps (즉, 45 Mbps 수준인 T3급 이상, 설계회로의 최대 지연 시간이 20ns 이하인 조건) 출력 수열이 발생될 수 있음을 확인하였다. 마지막으로, FPGA/VHDL 설계회로를 Lucent ASIC 소자 ($LV160C,\;0.13{\mu}m\;CMOS\;&\;1.5v\;technology$)로 설계 변환 및 타이밍 시뮬레이션한 결과 최대 지연시간이 1.8ns 이하였고, 500 Mbps 이상의 고속화가 가능함을 확인하였다.

• Journal of IKEEE
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• v.24 no.4
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• pp.1074-1080
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• 2020

This paper proposes a digitally controlled buck converter insensitive to process, voltage and temperature and capable of three modes of operation depending on the state of the output voltage. Conventional digital-controlled buck converters utilized A/D converters, counters and delay line circuits for accurate output voltage control, resulting in increasing the number of counter and delay line bits. This problem can be resolved by employing the 8-bit and 16-bit bidirectional shift registers, and this design technique leads a buck converter to be able to control duty ratio up to 128-bit resolution. The proposed buck converter was designed and fabricated with a CMOS 180 nano-meter 1-poly 6-metal process, generating an output voltage of 0.9 to 1.8V with the input voltage range of 2.7V to 3.6V, a ripple voltage of 30mV, and a power efficiency of up to 92.3%. The transient response speed of the proposed circuit was measured to be 4us.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.05a
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• pp.128-128
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• 2012

Korea institute of materials science (KIMS) has researched an anode layer linear ion source (ALIS) for various roll-to-roll treatment processes. The ALIS can be used to Ar ion beam (1~2 keV) treatment, and diamond-like carbon coating and so on. The treatment width of ALIS is 500 mm with a uniformity below 5 % (=(Max-min)/(Max+min)). We also demonstrate the status of development of ALIS in a roll-to-roll industry.