• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.35-38
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• 2005

Treatise that see designed MDS block newly algorithm itself is concise and improve the speed of Twofish cryptographic algorithm that easy of implement is good but the processing speed has slow shortcoming than Rijndael cryptographic algorithm Problem of speed decline by a bottle-neck phenomenon of processing process existed as block that designed MDS block occupies critical path of Twofish cryptographic system Multiplication arithmetic that is used by operator in this MDS convex using LUT arithmetic and modulo-2 arithmetic speed decline and a bottle-neck phenomenon about MDS itself remove. Twofish cryptographic system including MDS block designed newly by these result confirmed that bing elevation of the processing speed about $10\%$ than existing Twofish cryptographic system.

• Journal of the Korea Society of Computer and Information
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• v.10 no.5 s.37
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• pp.109-114
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• 2005

Twofish cryptographic algorithm is concise algorithm itself than Rijndael cryptographic algorithm as AES, and easy of implementation is good, but the processing speed has slow shortcoming. Therefore this paper designed improved MDS block to improve Twofish cryptographic algorithm's speed. Problem of speed decline by a bottle-neck Phenomenon of the Processing speed existed as block that existing MDS block occupies Twofish cryptosystem's critical path. To reduce multiplication that is used by operator in MDS block this Paper removed a bottle-neck phenomenon and low-speed about MDS itself using LUT operation and modulo-2 operation. Twofish cryptosystem including modified MDS block designed by these result confirmed that bring elevation of the processing speed about 10$\%$ than existing Twofish cryptosystem.

• The Journal of the Korea institute of electronic communication sciences
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• v.2 no.2
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• pp.118-122
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• 2007

The previous security system was PCI way which has many difficulties for PC novices to use. Moreover the security programs in use are mostly unverified ones as they are using cracks, and are exposed to attacks such as hackers and viruses. Therefore this thesis describes to design the security system of Twofish cryptographic algorithm using USB, which it can be used in general-purpose computers and users can handle it with ease. Users can easily use the security system by using this USB and it is applicable to various security systems that Twofish cryptographic algorithm used in the security system by having variable key length. Also the efficiency of the system can be enhanced as it can perform both encryption and decryption and it has a benefit of downsizing hardware.

• Journal of the Korea Society of Computer and Information
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• v.10 no.3 s.35
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• pp.183-188
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• 2005

Parallel processing in block cryptographic algorithm is difficult, because Feistel structure that is basis structure of block cryptographic algorithm is sequential processing structure. Therefore this paper changes these sequential processing structure and Feistel structure made parallel processing to be possible. This paper that apply this modified structure designed DES that have parallel Feistel structure. Proposed parallel Feistel structure could prove greatly block cryptographic algorithm's performance such as DES and so on that could not but have trade-off relation the data processing speed and data security interval because block cryptographic algorithm can not use pipeline method because of itself structural problem. Therefore, modified Feistel structure is going to display more superior security function and processing ability of high speed than now in case apply way that is proposed to SEED, AES's Rijndael, Twofish etc. that apply Feistel structure.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.5
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• pp.2680-2700
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• 2017

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.