• 제목/요약/키워드: Two-stacked

검색결과 277건 처리시간 0.024초

적층형 필라멘트와 방사형 필라멘트 구조를 갖는 원형 초전도선의 결합손실 (Coouping Losses of the Round HTS Wires with Stacked Filaments and Radial Filaments)

  • 신정욱;차귀수;이지광;한송엽
    • 한국초전도ㆍ저온공학회논문지
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    • 제2권1호
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    • pp.40-44
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    • 2000
  • The round HTS wire is easier to handle than the rectangular HTS tape. This paper describes the coupling losses of the round HTS wires by finite element method. Effect of the round HTS wire are considered. Two types of Filaments arrangement, stacked filament and radial filaments, are considered. Calculation results show that coupling losses of the round HTS wire vary only a little with the direction of external magnetic field.

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An L-band Stacked SOI CMOS Amplifier

  • Kim, Young-Gi;Hwang, Jae-Yeon
    • 전기전자학회논문지
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    • 제20권3호
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    • pp.279-284
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    • 2016
  • This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm. This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm saturated output power with a 16 % maximum Power Added Efficiency (PAE). A bond wire fine tuning technology enables the amplifier a 23.67 dBm saturated output power with a 20.4 % maximum PAE. The die area is $1.9mm{\times}0.6mm$.

Characterization of stacked geotextile tube structure using digital image correlation

  • Dong-Ju Kim;Dong Geon Son;Jong-Sub Lee;Thomas H.-K. Kang;Tae Sup Yun;Yong-Hoon Byun
    • Computers and Concrete
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    • 제31권5호
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    • pp.385-394
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    • 2023
  • Displacement is an important element for evaluating the stability and failure mechanism of hydraulic structures. Digital image correlation (DIC) is a useful technique to measure a three-dimensional displacement field using two cameras without any contact with test material. The objective of this study is to evaluate the behavior of stacked geotextile tubes using the DIC technique. Geotextile tubes are stacked to build a small-scale temporary dam model to exclude water from a specific area. The horizontal and vertical displacements of four stacked geotextile tubes are monitored using a dual camera system according to the upstream water level. The geotextile tubes are prepared with two different fill materials. For each dam model, the interface layers between upper and lower geotextile tubes are either unreinforced or reinforced with a cementitious binder. The displacement of stacked geotextile tubes is measured to analyze the behavior of geotextile tubes. Experimental results show that as upstream water level increases, horizontal and vertical displacements at each layer of geotextile tubes initially increase with water level, and then remain almost constant until the subsequent water level. The displacement of stacked geotextile tubes depends on the type of fill material and interfacial reinforcement with a cementitious binder. Thus, the proposed DIC technique can be effectively used to evaluate the behavior of a hydraulic structure, which consists of geotextile tubes.

A Numerically Efficient Full Wave Analysis of Circular Resonators Microbandes Stacked Involving Multimetallisations

  • Chebbara, F.;Fortaki, T.
    • Journal of Electrical Engineering and Technology
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    • 제10권1호
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    • pp.314-319
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    • 2015
  • The conventional geometry of a plate microstrip resonator is made up of a single metallic patch, which is printed on a monolayer dielectric substrate. Its arrangement is simple and easy to make, but it is limited in its functional abilities. Many searches have been realized to improve the bandwidth and the gain of the microstrip resonators. Among the various configurations proposed in the open literature, the stacked geometry seems to be very promising. By appropriate design, it is able to provide the operation in dual frequency mode, wide bandwidth enough and high gain. The theoretical investigations of structures composed of two stacked anti-reflection coatings, enhanced metallic coatings are available in the literature, however, for the stacked configurations involving three metallic coatings or more, not to exact or approximate analysis was conducted due to the complexity of the structure.

탄성파반자료자료의 경사보정 연구 (A Study on Dip-Moveout of Seismic Reflection Data)

  • 양승진
    • 자원환경지질
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    • 제32권5호
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    • pp.495-502
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    • 1999
  • Common-mid-point (CMP) seismic data on a dipping layer have have a stacking different from a horizontal layer velocity and the reflection points on data are dispersed to many positions. Therefore, the CMP data are not stacked well by the conventional stacking method using the horizontal layer velocity. The CMP gather can ideally stacked by applying dip-moveout(DMO) processing. Hence, modern seismic processing indludes DMO as an essential routine step. DMO processing techniques are broadly categorized by two, Fourier transform and integral methods, each of which has many different computational schemes. In this study, the dip-decomposition technique of the Fourier transform method is used to test the DMO effect on the synthetic scismic data generated for dipping structures. Each of constnat offset sections NMO corrected by using the layer velocity of the model and DMO processed. The resulting zero-offset sections for many offsets are stacked. The stacked sections with DMO processing show the structural boundaries of the models much better than those without DMO processing.

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Spatial Distribution of Localized Charge Carriers in SONOS Memory Cells

  • Kim Byung-Cheul
    • Journal of information and communication convergence engineering
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    • 제4권2호
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    • pp.84-87
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    • 2006
  • Lateral distributions of locally injected electrons and holes in an oxide-nitride-oxide (ONO) dielectric stack of two different silicon-oxide-nitride-oxide-silicon (SONOS) memory cells are evaluated by single-junction charge pumping technique. Spatial distribution of electrons injected by channel hot electron (CHE) for programming is limited to length of the ONO region in a locally ONO stacked cell, while is spread widely along with channel in a fully ONO stacked cell. Hot-holes generated by band-to-band tunneling for erasing are trapped into the oxide as well as the ONO stack in the locally ONO stacked cell.

HTS 케이블용 은시스 Bi-2223 테이프 및 원통형 적층 도체의 상전도 영역전파 특성 (Normal Zone Propagation Properties of Ag Sheathed Bi-2223 Tape for HTS Cable and Cylindrical Stacked Conductor)

  • 이병성;김영석;장현만;백승명;김상현
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2000년도 추계학술대회 논문집
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    • pp.448-451
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    • 2000
  • Normal zone propagation(NZP) characteristics were investigated on Ag sheathed Bi-2223 tape and cylindrical stacked conductor. Normal zone propagation(N2P) experiments with tape were conducted with refrigerator in temperature from 45 K to 77 K, 0 T. Cylindrical stacked conductor was molding with epoxy and experiments were conducted with adiabatic condition in $LN_2$. NZP velocities of tape with two condition of DC and AC were almost same at each temperature. NZP velocities of cylindrical stacked conductor were 1.9-2.4 cdsec in $LN_2$. Numerical analysis was carried out by a one-dimensional heat balance equation. As a result, simulated results of NZP velocity with Bi-2223 tape were similar to experimental results in DC.

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An Optimized Stacked Driver for Synchronous Buck Converter

  • Lee, Dong-Keon;Lee, Sung-Chul;Jeong, Hang-Geun
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제12권2호
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    • pp.186-192
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    • 2012
  • Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

Extension of the Dynamic Range in the CMOS Active Pixel Sensor Using a Stacked Photodiode and Feedback Structure

  • Jo, Sung-Hyun;Lee, Hee Ho;Bae, Myunghan;Lee, Minho;Kim, Ju-Yeong;Choi, Pyung;Shin, Jang-Kyoo
    • 센서학회지
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    • 제22권4호
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    • pp.256-261
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    • 2013
  • This paper presents an extension of the dynamic range in a complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) using a stacked photodiode and feedback structure. The proposed APS is composed of two additional MOSFETs and stacked P+/N-well/P-sub photodiodes as compared with a conventional APS. Using the proposed technique, the sensor can improve the spectral response and dynamic range. The spectral response is improved using an additional stacked P+/N-well photodiode, and the dynamic range is increased using the feedback structure. Although the size of the pixel is slightly larger than that of a conventional three-transistor APS, control of the dynamic range is much easier than that of the conventional methods using the feedback structure. The simulation and measurement results for the proposed APS demonstrate a wide dynamic range feature. The maximum dynamic range of the proposed sensor is greater than 103 dB. The designed circuit is fabricated by the $0.35-{\mu}m$ 2-poly 4-metal standard CMOS process, and its characteristics are evaluated.

Atomic Resolution Scanning Transmission Electron Microscopy of Two-Dimensional Layered Transition Metal Dichalcogenides

  • Lu, Ning;Wang, Jinguo;Oviedo, uan Pablo;Lian, Guoda;Kim, Moon Jea
    • Applied Microscopy
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    • 제45권4호
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    • pp.225-229
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    • 2015
  • Transition metal dichalcogenides (TMDs) are a class of two-dimensional (2D) materials that have attracted growing interest because of their promising applications. The properties of TMDs strongly depend on the crystalline structure and the number and stacking sequence of layers in their crystals and thin films. Though electrical, mechanical, and magnetic studies of 2D materials are being conducted, there is an evident lack of direct atom-by-atom visualization, limiting insight on these highly exciting material systems. Herein, we present our recent studies on the characterization of 2D layered materials by means of aberration corrected scanning transmission electron microscopy (STEM), in particular via high angle annular dark field (HAADF) imaging. We have identified the atomic arrangements and defects in 2H stacked TMDs, 1T stacked TMDs, distorted 1T stacked TMDs, and vertically integrated heterojunctions of 2D TMDs crystals.