• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.192-198
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• 2017

In this paper, we propose a novel double gate vertical channel tunneling field effect transistor (DVTFET) with a dielectric sidewall and optimization characteristics. The dielectric sidewall is applied to the gate region to reduced ambipolar voltage ($V_{amb}$) and double gate structure is applied to improve on-current ($I_{ON}$) and subthreshold swing (SS). We discussed the fin width ($W_S$), body doping concentration, sidewall width ($W_{side}$), drain and gate underlap distance ($X_d$), source doping distance ($X_S$) and pocket doping length ($X_P$) of DVTFET. Each of device performance is investigated with various device parameter variations. To maximize device performance, we apply the optimum values obtained in the above discussion of a optimization simulation. The optimum results are steep SS of 32.6 mV/dec, high $I_{ON}$ of $1.2{\times}10^{-3}A/{\mu}m$ and low $V_{amb}$ of -2.0 V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.7
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• pp.615-619
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• 2008

A molecular memory device which has a structure of Al/$Al_2O_3$/ASA-15 LB monolayer/Ti/Al device, was fabricated. To study a charge transfer mechanism of molecular memory devices, current density-voltage (J-V) characteristics were measured at an increasing temperature range from 10 K to 300 K with an interval of 30 K. Strong temperature-dependent electrical property and tunneling through organic monolayer at low bias (below 0.5 V) were appeared. These experimental data were fitted by using a theoretical formula such as the Simmons model. In comparison between the theoretical and the experimental results, it was verified that the fitting results using the Simmons model about direct tunneling was fairly fitted below 0.5 V at both 300 K and 10 K. Hopping conduction was also dominant at all voltage range above 200 K due to charges trapped by defects located within the dielectric stack, including the $Al_2O_3$, organic monolayer and Ti interfaces.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.172-178
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• 2016

In this paper, we propose a sub-10 nm Ge/GaAs heterojunction-based tunneling field-effect transistor (TFET) with vertical band-to-band tunneling (BBT) operation for ultra-low-power (LP) applications. We design a stack structure that is based on the Ge/GaAs heterojunction to realize the vertical BBT operation. The use of vertical BBT operations in devices results in excellent subthreshold characteristics with a reduction in the drain-induced barrier thinning (DIBT) phenomenon. The proposed device with a channel length ($L_{ch}$) of 5 nm exhibits outstanding LP performance with a subthreshold swing (S) of 29.1 mV/dec and an off-state current ($I_{off}$) of $1.12{\times}10^{-11}A/{\mu}m$. In addition, the use of the highk spacer dielectric $HfO_2$ improves the on-state current ($I_{on}$) with an intrinsic delay time (${\tau}$) because of a higher fringing field. We demonstrate a sub-10 nm LP switching device that realizes a good S and lower $I_{off}$ at a lower supply voltage ($V_{DD}$) of 0.2 V.

• Journal of Magnetics
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• v.10 no.2
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• pp.66-70
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• 2005

The junction properties between the ferromagnet (FM) and two-dimensional electron gas (2DEG) system are crucial to develop spin electronic devices. Two types of 2DEG layer, InAs and GaAs channel heterostructures, are fabricated to compare the junction properties of the two systems. InAs-based 2DEG layer with low trans-mission barrier contacts FM and shows ohmic behavior. GaAs-based 2DEG layer with $Al_2O_3$ tunneling layer is also prepared. During heat treatment at the furnace, arsenic gas was evaporated and top AlAs layer was converted to aluminum oxide layer. This new method of forming spin injection barrier on 2DEG system is very efficient to obtain tunneling behavior. In the potentiometric measurement, spin-orbit coupling of 2DEG layer is observed in the interface between FM and InAs channel 2DEG layers, which proves the efficient junction property of spin injection barrier.

• Journal of the Semiconductor & Display Technology
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• v.17 no.4
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• pp.6-10
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• 2018

Organic light emitting devices have attracted the attention of many people because of their high potential for self-emission and flexible display devices. However, due to limitations in device efficiency and lifetime, partial commercialization is underway. In this paper, we have investigated the electrical conduction mechanism of the organic light emitting device by the temperature and the thickness of the light emitting layer through the current - voltage characteristics with respect to the conduction mechanism directly affecting the efficiency and lifetime of the organic light emitting device. Through the study, it was found that the conduction in the low electric field region is caused by the movement of the heat excited charge in the ohmic region and the tunneling of the electric charge due to the high electric field in the high electric field region.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.12
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• pp.2188-2194
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• 2008

Home network is the connection and communication of several electronic and electrical devices at hone with the integration of several technologies like Ethernet, wireless, phone line and power-line at the residential gateway to the internet. This internet based home network can be accessed from any part of the world through any device by any poison via internet. Since home network is developed for comfortable and safe life of home users, the information flow to/from home network needs to be private. Hence the remote access of the home network must be secured. This paper analyses two secure tunneling methods, voluntary and compulsory for L2TP(Layer Two Tunneling Protocol) based VPN(Virtual Private Network) for secure remote access of the home network.

• Journal of information and communication convergence engineering
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• v.19 no.4
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• pp.263-268
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• 2021

Although the compact capacitance model of point tunneling types of tunneling field-effect transistors (TFET) has been proposed, those of line tunneling types of TFETs have not been reported. In this study, a compact capacitance model of an L-shaped TFET (LTFET), a line tunneling type of TFET, is proposed using the previously developed surface potentials and current models of P- and L-type LTFETs. The Verilog-A LTFET model for simulation program with integrated circuit emphasis (SPICE) was also developed to verify the validation of the compact LTFET model including the capacitance model. The SPICE simulation results using the Verilog-A LTFET were compared to those obtained using a technology computer-aided-design (TCAD) device simulator. The current-voltage characteristics and capacitance-voltage characteristics of N and P-LTFETs were consistent for all operational bias. The voltage transfer characteristics and transient response of the inverter circuit comprising N and P-LTFETs in series were verified with the TCAD mixed-mode simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.182-189
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• 2011

In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of III-V TFETs, a Type-I heterojunction tunneling field-effect transistor (I-HTFET) adopting $Ge-Al_xGa_{1-x}As-Ge$ system has been optimized by simulation in terms of aluminum (Al) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (HP) logic technology can be achieved by the proposed device. The optimum Al composition turned out to be around 20% (x=0.2).

• Electrical & Electronic Materials
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• v.8 no.6
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• pp.727-736
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• 1995

This paper examines the characteristics and physical properties of the scaled MONOS nonvolatile memory device for low programming voltage EEPROM. The capacitor-type MONOS memory devices with the nitride thicknesses ranging from 41.angs. to 600.angs. have been fabricated. As a result, the 5V-programmable MONOS device has been obtained with a 20ms programming time by scaling the nitride thickness to 57.angs. with a tunneling oxide thickness of 19.angs. and a blocking oxide thickness of 20.angs.. Measurement results of the quasi-static C-V curves indicate, after 10$\^$6/ write/erase cycles, that the devices are degraded due to the increase of the silicon-tunneling oxide interface traps. The 10-year retention is impossible for the device with a nitride less than 129.angs.. However, the MONOS memory device with 10-year retentivity has been obtained by increasing the blocking oxide thickness to 47.angs.. Also, the memory traps such as the nitride bulk trap and the blocking oxide-nitride interface trap have been investigated by measuring the maximum flatband voltage shift and analyzing through the best fitting method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.572-578
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• 2014

In order to overcome small current drivability of a tunneling field-effect transistor (TFET), a TFET using Schottky barrier (SBTFET) is proposed. The proposed device has a metal source region unlike the conventional TFET. In addition, dopant segregation technology between the source and channel region is applied to reduce tunneling resistance. For TFET fabrication, spacer technique is adopted to enable self-aligned process because the SBTFET consists of source and drain with different types. Also the control device which has a doped source region is made to compare the electrical characteristics with those of the SBTFET. From the measured results, the SBTFET shows better on/off switching property than the control device. The observed drive current is larger than those of the previously reported TFET. Also, short-channel effects (SCEs) are investigated through the comparison of electrical characteristics between the long- and short-channel SBTFET.