• 한국전기전자재료학회논문지
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• 제17권1호
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• pp.21-26
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• 2004

Ultra-thin silicon dioxides were grown on p-type(100) oriented silicon employing rapid thermal dry oxidation technique at the temperature range of 850∼1050 $^{\circ}C$. The growth rate of the ultra-thin film was fitted well with tile model which was proposed recently by da Silva ＆ Stosic. The capacitance-voltage, current-voltage, characteristics were used to study the electrical properties of these thin oxides. The minimum interface state density around the midgap of the MOS capacitor having oxide thickness of 111.6 $\AA$ derived from the C-V curve was ranged from 6 to 10${\times}$10$^{10}$ /$\textrm{cm}^2$eV.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.156-161
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• 2017

This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

• 전자공학회논문지T
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• 제35T권1호
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• pp.29-32
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• 1998

실리콘 산화막에서 저레벨 누설전류를 조사하였다. 저레벨 누설전류는 전이요소와 직류요소로 구성되어 있다. 전이요소는 스트레스에 의해 두 계면트랩 가까이 발생된 트랩의 충방전에 의한 터널링으로 나타났으며 직류요소는 산화막을 통한 트랩 어시스트 터널링으로 나타났다 그리고 저레벨 누설전류는 산화막에서 발생된 트랩의 수에 비례하였다. 저레벨 누설전류는 트랩의 충방전 누설전류이며 비휘발성 소자의 데이터 유지능력에 영향을 주었다.

• Transactions on Electrical and Electronic Materials
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• 제13권3호
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• pp.162-164
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• 2012

In this study, we fabricate Pt nanoparticle (NP)-embedded MOS capacitors at room temperature and investigate their memory characteristics. The Pt NPs are separated from each other and situated between the tunnel and control oxide layers. The average size and density of the Pt NPs are 4 nm and $3.2{\times}10^{12}cm^{-2}$, respectively. Counterclockwise hysteresis with a width of 3.3 V is observed in the high-frequency capacitance-voltage curve of the Pt NP-embedded MOS capacitor. Moreover, more than 93% of the charge remains even after $10^4$ s.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.122-122
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• 2008

Recently, Metal/Alumina/Silicon-Nitride/Silicon-Oxide/Silicon (MANOS) structures are one of the most attractive candidates to realize vertical scaling of high-density NAND flash memory [1]. However, as ANO layers are miniaturized, negative and positive bias temperature instability (NBTI/PBTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density increase, ${\Delta}D_{it}$, the gate leakage current, ${\Delta}I_G$. and the retention characteristics, in MONOS capacitors, becomes an important issue in terms of reliability. It is well known that tunnel oxide degradation is a result of the oxide and interfacial traps generation during FN (Fowler-Nordheim) stress [2]. Because the bias temperature stress causes an increase of both interfacial-traps and fixed oxide charge could be a factor, witch can degrade device reliability during the program and erase operation. However, few studies on NBTI/PBTI have been conducted on improving the reliability of MONOS devices. In this work, we investigate the effect of post-annealing gas on bias temperature instability (BTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density shift, ${\Delta}I_G$ retention characteristics, and the gate leakage current characteristics of MANOS capacitors. MANOS samples annealed at $950^{\circ}C$ for 30 s by a rapid thermal process were treated via additional annealing in a furnace, using annealing gases $N_2$ and $N_2-H_2$ (2 % hydrogen and 98 % nitrogen mixture gases) at $450^{\circ}C$ for 30 min. MANOS samples annealed in $N_2-H_2$ ambient had the lowest flat band voltage shift, ${\Delta}V_{FB}$ = 1.09/0.63 V at the program/erase state, and the good retention characteristics, 123/84 mV/decade at the program/erase state more than the sample annealed at $N_2$ ambient.

• Journal of Magnetics
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• 제11권1호
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• pp.25-29
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• 2006

Recent experiments have demonstrated high TMR ratios in MTJs with the MgO barrier [1,2]. The CoFeB/MgO/CoFeB junctions showed better properties than the CoFe/MgO/CoFe junctions because the MgO layer had a good crystalline structure with (001) texture and smooth and sharp interface between CoFeB/MgO [3]. The amorphous CoFeB with 20 at%B starts the crystallization at $340^{\circ}C$ [4] and this crystallization of the CoFeB helps obtaining the high TMR ratio. In this work, the compositional changes in the MgO barrier and at the interface of CoFeB/MgO/CoFeB after the CoFeB crystallization were studied in annealed MTJs. XPS depth profiles were utilized. TEM analyses showed that the MgO barrier had (100) texture on CoFeB in the junctions. B in the bottom CoFeB layer diffused into the MgO barrier and B-oxide was formed at the interface of CoFeB/MgO/CoFeB after the CoFeB crystallization.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.167-167
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• 2011

Magnetic random access memory (MRAM) is one of the prospective semiconductor memories for next generation. It has the excellent features including nonvolatility, fast access time, unlimited read/write endurance, low operating voltage, and high storage density. MRAM consists of magnetic tunnel junction (MTJ) stack and complementary metal-oxide semiconductor (CMOS). The MTJ stack is composed of various magnetic materials, metals, and a tunneling barrier layer. For the successful realization of high density MRAM, the etching process of magnetic materials should be developed. Among various magnetic materials, FePt has been used for pinned layer of MTJ stack. The previous etch study of FePt magnetic thin films was carried out using $CH_4/O_2/NH_3$. It reported only the etch characteristics with respect to the variation of RF bias powers. In this study, the etch characteristics of FePt thin films have been investigated using an inductively coupled plasma reactive ion etcher in various etch chemistries containing $CH_4$/Ar and $CH_4/O_2/Ar$ gas mixes. TiN thin film was employed as a hard mask. FePt thin films are etched by varying the gas concentration. The etch characteristics have been investigated in terms of etch rate, etch selectivity and etch profile. Furthermore, x-ray photoelectron spectroscopy is applied to elucidate the etch mechanism of FePt thin films in $CH_4$/Ar and $CH_4/O_2/Ar$ chemistries.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.408-408
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• 2012

It is well known that magnetic random access memory (MRAM) is nonvolatile memory devices using ferromagnetic materials. MRAM has the merits such as fast access time, unlimited read/write endurance and nonvolatility. Although DRAM has many advantages containing high storage density, fast access time and low power consumption, it becomes volatile when the power is turned off. Owing to the attractive advantages of MRAM, MRAM is being spotlighted as an alternative device in the future. MRAM consists of magnetic tunnel junction (MTJ) stack and complementary metal- oxide semiconductor (CMOS). MTJ stacks are composed of various magnetic materials. FePt thin films are used as a pinned layer of MTJ stack. Up to date, an inductively coupled plasma reactive ion etching (ICPRIE) method of MTJ stacks showed better results in terms of etch rate and etch profile than any other methods such as ion milling, chemical assisted ion etching (CAIE), reactive ion etching (RIE). In order to improve etch profiles without redepositon, a better etching process of MTJ stack needs to be developed by using different etch gases and etch parameters. In this research, influences of $O_2$ gas on the etching characteristics of FePt thin films were investigated. FePt thin films were etched using ICPRIE in $CH_4/O_2/Ar$ gas mix. The etch rate and the etch selectivity were investigated in various $O_2$ concentrations. The etch profiles were studied in varying etch parameters such as coil rf power, dc-bias voltage, and gas pressure. TiN was employed as a hard mask. For observation etch profiles, field emission scanning electron microscopy (FESEM) was used.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.387-387
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• 2013

Currently, the flash memory and the dynamic random access memory (DRAM) have been used in a variety of applications. However, the downsizing of devices and the increasing density of recording medias are now in progress. So there are many demands for development of new semiconductor memory for next generation. Magnetic random access memory (MRAM) is one of the prospective semiconductor memories with excellent features including non-volatility, fast access time, unlimited read/write endurance, low operating voltage, and high storage density. MRAM is composed of magnetic tunnel junction (MTJ) stack and complementary metal-oxide semiconductor (CMOS). The MTJ stack consists of various magnetic materials, metals, and a tunneling barrier layer. Recently, MgO thin films have attracted a great attention as the prominent candidates for a tunneling barrier layer in the MTJ stack instead of the conventional Al2O3 films, because it has low Gibbs energy, low dielectric constant and high tunneling magnetoresistance value. For the successful etching of high density MRAM, the etching characteristics of MgO thin films as a tunneling barrier layer should be developed. In this study, the etch characteristics of MgO thin films have been investigated in various gas mixes using an inductively coupled plasma reactive ion etching (ICPRIE). The Cl2/Ar, CH3OH/Ar, and CH4/Ar gas mix were employed to find an optimized etching gas for MgO thin film etching. TiN thin films were employed as a hard mask to increase the etch selectivity. The etch rates were obtained using surface profilometer and etch profiles were observed by using the field emission scanning electron microscopy (FESEM).

• 마이크로전자및패키징학회지
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• 제24권3호
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• pp.7-11
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• 2017

본 논문은 3차원 낸드 플래쉬 기억 소자에 적용을 위해 소노스(SONOS) 형태로 기억 저장 절연막을 채용하고 채널로 폴리실리콘을 사용한 박막형 트랜지스터에 대해 연구하였다. 셀의 source/drain에는 불순물을 주입 하지 않았고, 셀 양 끝단에는 선택 트랜지스터를 배치하였다. 셀의 채널과 선택 트랜지스터의 source/drain 불순물 농도 변화에 대한 평가를 진행하여 공정 최적화를 하였다. 선택 트랜지스터의 농도 증가 시 채널 전류의 상승 및 삭제특성이 개선됨을 확인 하였는데 이는 GIDL에 의한 홀 생성이 증가하였기 때문이다. 최적화된 공정 변수에 대해 삭제와 쓰기 후 문턱전압의 프로그램 윈도우는 대략 2.5V를 얻었다. 터널 산화막 공정 온도에 대한 평가 결과 온도 증가 시 swing 및 신뢰성 항목인 bake 결과가 개선됨을 확인하였다.