• 제어로봇시스템학회:학술대회논문집
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• 1995.10a
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• pp.146-149
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• 1995

A new method for grouping of relevant and equivalent inputs of a logical circuit was proposed by the authors by making use of pseudorandom M-sequence correlation. The authors show in this paper that it is possible to estimate the input grouping from a part of correlation functions when we admit small percentage of error, whereas it is impossible to reduce the data necessary to estimate the grouping by use of the truth table method. For example in case of 30-input logic circuit, the number of correlation functions necessary to calculate can be reducible from 1.07 * 10$^{9}$ to 465.

• The Journal of the Korea Contents Association
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• v.18 no.1
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• pp.10-18
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• 2018

This paper presents a method to resynthesize logic of a programmed FPGA from a bitstream file that is a downloaded file for Xilinx FPGA (Field Programmable Gate Array). It focuses on reconfiguring the LUT (Look Up Table) logic. The bitstream data is compared and analyzed considering various situations and various input variables such as composing other logics using the same netlist or synthesizing the same logic at various positions to find a structure of the bitstream. Based on the analyzed bitstream, we construct a truth table of the LUT by implementing various logic for one LUT. The proposed algorithm extracts the logic of the LUT based on the truth table of the generated LUT and the bitstream. The algorithm determines the input and output pins used to implement the logic in the LUT. As a result, we extract a gate level logic from a bitstream file for the targeted Xillinx FPGA.

• The Journal of the Korea Contents Association
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• v.8 no.4
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• pp.86-91
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• 2008

To present the design procedure of discretized 8-bit tent map executing the transformation of tent function which is one of the chaotic functions, first, the truth table of discretized tent map was written, and then according to the simplified Boolean algebra equations obtained from the truth table, the discretized map is implemented with the exclusive logic gate as a real hardware. The discretized tent map circuit which provides the feedback circuit for generating the period-8 states relevant to the 8-bit finite precision is also designed and presented in this paper. Furthermore, it might be used stream cipher system with a new key-stream circuit for generate of chaotic binary sequence.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.107-115
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• 2014

The reduced-bit transform based bit-plane matching algorithm (BPM) can obtain the block matching result through its simple calculation and hardware design compared to the conventional block matching algorithms (BMAs), but the block matching accuracy of BPMs is somewhat low. In this paper, reduced-bit transform based sum of the absolute difference (R-SAD) is proposed to improve the block matching accuracy in comparison with the conventional BPMs and it is shown that the matching process can be obtained using the logical operations. Firstly, this method transforms the current and the reference images into their respective 2-bit images and then a truth table is obtained from the relation between input and output 2-bit images. Next, a truth table is simplified by Karnaugh map and the absolute difference is calculated by using simple logical operations. Finally, the simulation results show that the proposed R-SAD can obtain higher accuracy in block matching results compared to the conventional BPMs through the PSNR analysis in the motion compensation experiments.

• Journal of the Korea Safety Management & Science
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• v.17 no.4
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• pp.381-396
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• 2015

The study proposes multiple TRIZ contradiction solution strategies for addressing PC (Physical Contradiction) and TC (Technical Contradiction) by implementing TRIZ cause-and-effect tree. The problem associated with TC of the ends is solved by PC of means which employs a causal relationship between causes and effects. The TRIZ contradiction solution strategies demonstrated in this research are classified into 3 types of combined strategy as follows: 1. To-Be PC and AS-Is PC, 2.To-Be PC and As-Is TC, 3.As-Is PC and To-Be TC. The combined strategy of To-Be PC and As-Is PC is similar to a divide-and-conquer technique. This strategy adopts parallel strategies using 4 separation principles in time, in space, between parts and the whole, and upon condition of two reversed-PCs. Moreover, its application elucidates the conflict relationship of two TCs from the study. The integrated 4 separation principles and 40 inventive principles present an effective synergy effect from the combination, and further addresses the problems in the TRIZ contradiction resolution strategies. Combined strategy of To-Be PC and As-Is TC implements the 40 inventive principles that To-Be PC of the means resolves the As-Is TC of the ends. Combined strategy of As-Is PC and To-Be TC also uses inventive principles to the As-Is PC of the means to solve the To-Be TC of the ends. In addition, propositional and logical relationship of necessary and sufficient conditions between TC and PC is used to support the validity of 3 TRIZ contradiction solution strategies. In addition, 3 other strategies of necessary and sufficient conditions validate the contraposition relationship of the truth table. This study discusses TRIZ case studies from National Quality Circle Contest from the years between 2011 and 2014 to provide the usage guidelines of TRIZ contradiction solutions for quality purposes. Examining analysis from the case studies and investigating combined strategies allows the users to obtain comprehensive understanding.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.191-200
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• 2002

In this paper, we present the method transforming the interval functions into the truncated difference functions for multi-variable multi-valued functions and implementing the truncated difference functions to the multiple valued logic circuits with uniform patterns using the current mirror circuits and the inhibit circuits by current-mode CMOS. Also, we apply the presented methods to the implementation of circuits for additive truth table of 2-variable 4-valued MOD(4) and multiplicative truth table of 2-variable 4-valued finite fields GF(4). These circuits are simulated under 2${\mu}{\textrm}{m}$ CMOS standard technology, 15$mutextrm{A}$ unit current, and 3.3V power supply voltage using PSpice. The simulation results have shown the satisfying current characteristics. Both implemented circuits using current-mode CMOS have the uniform Patterns and the regularity of interconnection. Also, it is expansible for the variables of multiple valued logic functions and are suitable for VLSI implementation.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.6
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• pp.868-875
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• 1995

This paper presents a method of constructing the multiple-valued combinational logic systems(MVCLS) by decision diagram. The switching function truth table of MVCLS is transformed into canonical normal form of sum-of-products(SOP) with literals at first. Next, the canonical normal form of SOP is transfered into multiple-valued logic decision diagram(MVLDD). The selecting of variable ordering is very important in this stage. The MVLDDs are quite different from each other according to the variable ordering. Sometimes the inadequate variable ordering produces a very large size of MVLDD means the large size of circuit implementation. An algorithm for generating the proper variable ordering produce minimal MVLDD and an example shows the verity of the algorithm. The circuits are realized with T-gate acceording to the minimal MVLDD.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.10
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• pp.73-80
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• 1995

In this paper, a synthesis tool using matrix operations for designing multi-level Reed Muller circuits is described which has been named as MRM (Multi-level Reed Muller Minimizer). The synthesis method which uses matrix operations has advantages in effectively minimizing chip area, delay optimization and fault detection capability. However, it uses only truth-table type maps for inputs, synthesizing only small circuits. To overcome the weakness, our method accepts two-level description of a logic function. Since the number of cubes in the two-level description is small, the input matrix becomes small and large circuits can be synthesized. To convert two-level representations into multi-level ones, different input patterns are extracted to make a map which can be fed to the matrix operation procedure. Experimental results show better performance than previous methods. The matrix operation method presented in this paper is new to the society of Reed Muller circuits synthesis and provides solid mathematical foundations.

• Journal of Electrical Engineering and Technology
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• v.8 no.3
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• pp.572-580
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• 2013

Power metering and monitoring system is a basic element of Smart Grid technology. This paper proposes a new Non-Intrusive Load Monitoring (NILM) method for a residential buildings sector using the measured total active power consumption. Home electrical appliances are classified by ON/OFF state models, Multi-state models, and Composite models according to their operational characteristics observed by experiments. In order to disaggregate the operation and the power consumption of each model, an algorithm which includes a switching function, a truth table matrix, and a matching process is presented. Typical profiles of each appliances and disaggregation results are shown and classified. To improve the accuracy, a Time Lagging (TL) algorithm and a Permanent-On model (PO) algorithm are additionally proposed. The method is validated as comparing the simulation results to the experimental ones with high accuracy.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.6
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• pp.13-18
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• 1985

A set of utility programs for automatic generation, minimization and verification of high density PLA layout was developed, which includes equation-to-truth table translator, logic minimizer, PLA product term sorter, file generator for plotting stick diagram, dynamic CMOS PLA layout generator and bipartite row folded CMOS PLA layout generator. Size reduction is performed mainly by logic minimizer and bipartite row folder, and the maximal delay is reduced by sorter. The fOe for automatically generated layout is stored in CIF. Each program was written in Clanguage, and was run on VAX-11/750 (UNIX).