• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.229-229
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• 2010

With the scaling down of ultra large integrated circuits (ULSI) to the sub-50 nm technology node, the need for an ultra-thin, continuous and conformal diffusion barrier and Cu seed layer is increasing. However, diffusion barrier and Cu seed layer formation with a physical vapor deposition (PVD) method has become difficult as the technology node is reduced to 30 nm and beyond. Recent work on self-forming barrier processes using PVD Cu alloys have attracted great attention due to the capability of conformal ultra-thin barrier formation using a simple technique. However, as in the case of the conventional barrier and Cu seed layer, PVD of the Cu alloy seed layer will eventually encounter the difficulty in conformal deposition in narrow line trenches and via holes. Atomic layer deposition (ALD) has been known for its good step coverage and precise thickness control, and is a candidate technique for the formation of a thin conformal barrier layer and Cu seed layer. Conformal Cu-Mn seed layers were deposited by plasma enhanced atomic layer deposition (PEALD) at low temperature ($120^{\circ}C$), and the Mn content in the Cu-Mn alloys were controlled form 0 to approximately 10 atomic percent with various Mn precursor feeding times. Resistivity of the Cu-Mn alloy films decreased by annealing due to out-diffusion of Mn atoms. Out-diffused Mn atoms were segregated to the surface of the film and interface between a Cu-Mn alloy and $SiO_2$, resulting in self-formed $MnO_x$ and $MnSi_xO_y$, respectively. No inter-diffusion was observed between Cu and $SiO_2$ after annealing at $500^{\circ}C$ for 12 h, indicating an excellent diffusion barrier property of the $MnSi_xO_y$. The adhesion between Cu and $SiO_2$ was enhanced by the formation of $MnSi_xO_y$. Continuous and conductive Cu-Mn seed layers were deposited with PEALD into 32 nm $SiO_2$ trench, enabling a low temperature process, and the trench was perfectly filled using electrochemical plating (ECD) under conventional conditions. Thus, it is the resultant self-forming barrier process with PEALD Cu-Mn alloy film as a seed layer for plating Cu that has further potential to meet the requirement of the smaller than 30 nm node.

• ETRI Journal
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• v.35 no.3
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• pp.425-430
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• 2013

In this paper, we propose a triple-gate trench power MOSFET (TGRMOS) that is made through a modified RESURF stepped oxide (RSO) process, that is, the nitride_RSO process. The electrical characteristics of TGRMOSs, such as the blocking voltage ($BV_{DS}$) and on-state current ($I_{D,MAX}$), are strongly dependent on the gate configuration and its bias condition. In the nitride_RSO process, the thick single insulation layer ($SiO_2$) of a conventional RSO power MOSFET is changed to a multilayered insulator ($SiO_2/SiN_x/TEOS$). The inserted $SiN_x$ layer can create the selective etching of the TEOS layer between the gate oxide and poly-Si layers. After additional oxidation and the poly-Si filling processes, the gates are automatically separated into three parts. Moreover, to confirm the variation in the electrical properties of TGRMOSs, such as $BV_{DS}$ and $I_{D,MAX}$, simulation studies are performed on the function of the gate configurations and their bias conditions. $BV_{DS}$ and $I_{D,MAX}$ are controlled from 87 V to 152 V and from 0.14 mA to 0.24 mA at a 15-V gate voltage. This $I_{D,MAX}$ variation indicates the specific on-resistance modulation.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.2
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• pp.146-153
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• 2008

Integrated humidity sensor system with two stages operational amplifier has been designed and fabricated by $0.8{\mu}m$ analog mixed CMOS technology. The system (28 pin and $2mm{\times}4mm$) consisted of Wheatstone-bridge type humidity sensor, resistive type humidity sensor, temperature sensors and operational amplifier for signal amplification and process in one chip. The poly-nitride etch stop process has been tried to form the sensing area as well as trench in a standard CMOS process. This modified technique did not affect the CMOS devices in their essential characteristics and gave an allowance to fabricate the system on same chip by standard process. The operational amplifier showed the stable operation so that unity gain bandwidth was more than 5.46 MHz and slew rate was more than 10 V/uS, respectively. The drain current of n-channel humidity sensitive field effect transistor (HUSFET) increased from 0.54 mA to 0.68 mA as the relative humidity increased from 10 to 70 %RH.

• Journal of the Korean Vacuum Society
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• v.19 no.2
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• pp.91-95
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• 2010

A UV-enhanced atomic layer deposition (UV-ALD) process was developed to deposit $TiO_2$ thin films on Si substrates using titanium isopropoxide(TIP) and $H_2O$ as precursors with UV light. In the UV-ALD process, the surface reactions were found to be self-limiting and complementary enough to yield a uniform, conformal, pure $TiO_2$ thin film on Si substrates at room temperature. The UV light was very effective to obtain the high-quality $TiO_2$ thin films with good adhesive strength on Si substrates. The UV-ALD process was applied to produce uniform and conformal $TiO_2$ coats into deep trenches with high aspect ratio.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.10b
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• pp.441-442
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• 2002

Chemical mechanical polishing (CMP) is a manufacturing process that uses controlled wear to planarize dielectric and metallic layers on silicon wafers. CMP experiments revealed that a sub-ambient film pressure developed at the wafer/pad interface. Additionally, dishing occurs in CMP processes when the copper-in-trench lines are removed at a rate higher than the barrier layer. In order to study dishing across a stationary wafer during polishing, dishing maps were created. Since dishing is a function of the total contact pressure resulting from the applied load and the fluid pressure, the hydrodynamic pressure model was refined and used in an existing model to study copper dishing. Density maps, highlighting varying levels of dishing across the wafer face at different radial positions, were developed. This work will present the results.

• Korean Journal of Materials Research
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• v.6 no.5
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• pp.524-531
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• 1996

차세대 소자고립구조로서 연구되고 있는 trench isolation 공정 등에는 실리콘 식각이 요구되며 실리콘 식각 공정중에는 반응성 이온에 의해 격자결함이 발생할 수 있다. 이와같이 생성된 결함은 소자의 전기적 성질을 열화시키므로 열처리를 통하여 제거하여야만 한다. 따라서 본 연구에서는 Ar,Ar/H2 플라즈마로 격자결함을 인위적으로 발생시켜 20$0^{\circ}C$-110$0^{\circ}C$ 질소분위기에서 30분간 열처리에 따른 생성된 격자결함의 소거거동을 관찰하였다. 실리콘 표면에 Schottky 다이오드를 제작하여 I-V, C-V 특성을 측정하므로써 잔류하는 전기적인 손상의 정도를 평가하였다. Ar으로 식각한 경우에는 110$0^{\circ}C$ 30분간 열처리한 결과 모든 격자결함이 제거되나 Ar/H2로 식각한 경우에는 격자결함이 완전히 제거되지 않고 (111)적층결함이 남아있었다.

• Journal of the Korean Vacuum Society
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• v.11 no.3
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• pp.159-165
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• 2002

The physical properties of the TiN films deposited by ALD using $TiCl_4$and $NH_3$have been investigated. The TiN deposition rate is ~0.6 $\AA$ under an optimum deposition condition and the resistivity of the TiN films is 200~350 $\mu\Omega$cm . According to the XRD analysis results TiN films are crystallized in the ALD process window. AES analysis results show that the Cl impurity concentration in the TiN films is lower than 1 at% and that the atomic ratio of the TiN films is 1:1. Also it is found by SEM observation that the step coverage of the TiN films on which TiN films with trenches the aspect ratio of which is 10:1 is excellent.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.370-370
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• 2012

Feature size of Cu interconnects keep shrinking into several tens of nanometer level. For this reason, the Cu interconnects face challenging issues such as increase of electro-migration, line-width dependent electrical resistivity increase, and gap-filling difficulty in high aspect ratio structures. As the thickness of the Cu film decreases below 30 nm, the electrical resistivity is not any more constant, but rather exponential. Research on alloying with other elements have been started to inhibit such escalation in the electrical resistivity. A faint trace of Al added in Cu film by sputtering was reported to contribute to suppression of the increase of the electrical resistivity. From an industrial point of view, we introduced cyclic metal organic chemical vapor deposition (MOCVD) in order to control Al concentration in the Cu film more easily by controlling the delivery time ratio of Cu and Al precursors. The amount of alloying element could be lowered at level of below 1 at%. Process of the alloy formation was applied into gap-filling to evaluate the performance of the gap-filling. Voidless gap-filling even into high aspect ratio trenches was achieved. In-depth analysis will be discussed in detail.

• Journal of the Korea Society for Simulation
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• v.9 no.4
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• pp.51-58
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• 2000

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. The novel junction process scheme in sub-micron DRAM cell with STI(Shallow Trench Isolation) has been investigated to improve the tail component in the retention time distribution which is of great importance in DRAM characteristics. In this' paper, we propose the new implantation scheme by gate-related ion beam shadowing effect and buffer-enhanced ${\Delta}Rp$ (projected standard deviation) increase using buffered N-implantation with tilt and 4X(4 times)-rotation that is designed on the basis of the local-field-enhancement model of the tail component. We report an excellent tail improvement of the retention time distribution attributed to the reduction of electric field across the cell junction due to the redistribution of N-concentration which is Intentionally caused by ion Beam Shadowing and Buffering Effect using tilt implantation with 4X-rotation. And also, we suggest the least requirements for adoption of this new implantation scheme and the method to optimize the key parameters such as tilt angle, rotation number, Rp compensation and Nd/Na ratio. We used MEDICI Simulator to confirm the junction device characteristics. And measured the refresh time using the ADVAN Probe tester.

• Proceedings of the Korean Geotechical Society Conference
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• 2009.09a
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• pp.1275-1282
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• 2009

The tunnel excavations are used for construction of common utility tunnel, electric tunnel, communication line tunnel, water supply and public sewerage pile line in urban area. The trench cut methods were mainly used in the past, but now, tunneling method is more being used. The tunnel excavation method like as NATM, Messer-Shield, Semi-Shield Methods are being applied to small section tunnel in Korea. The actual construction results of seme-shield method are increasing due to simplified construction process and reduced noise and vibration. And also this method is being used frequently in waterway tunnel and construction of prevention flooding recently. The seme-shield method design guideline is absence except for electric line tunnel construction in Korea, because of the semi-shield method was developed in Europe and Japan. In the prescriptive design, engineer's subjects are tending to intervene, because of absence of standard and specification for details. Therefore, Design and Construction Problems of Semi-Shield Method were described and construction trouble was introduced for exam. These problem and construction troubles have to be examined thoroughly in advance.