• 한국분말재료학회지
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• 제24권6호
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• pp.464-471
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• 2017

A metal mesh TCE film is fabricated using a series of processes such as UV imprinting of a transparent trench pattern (with a width of $2-5{\mu}m$) onto a PET film, filling it with silver paste, wiping of the surface, and heat-curing the silver paste. In this work nanosized (40-50 nm) silver particles are synthesized and mixed with submicron (250-300 nm)-sized silver particles to prepare silver paste for the fabrication of metal mesh-type TCE films. The filling of these silver pastes into the patterned trench layer is examined using a specially designed filling machine and the rheological testing of the silver pastes. The wiping of the trench layer surface to remove any residual silver paste or particles is tested with various mixture solvents, and ethyl cellosolve acetate (ECA):DI water = 90:10 wt% is found to give the best result. The silver paste with 40-50 nm Ag:250-300 nm Ag in a 10:90 wt% mixture gives the highest electrical conductance. The metal mesh TCE film obtained with this silver paste in an optimized process exhibits a light transmittance of 90.4% and haze at 1.2%, which is suitable for TSP application.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.41-44
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• 2000

Ultra large scale integrated circuit(ULSI) & complementary metal oxide semiconductor(CMOS) circuits require gate electrode materials such as meta] silicides, titanium-silicide for gate oxides. Many previous authors have researched the improvements sub-micron gate oxide quality. However, little has been done on the electrical quality and reliability of ultra thin gates. In this research, we recommend novel shallow trench isolation structure and two step TiSi$_{2}$ formation for sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• 한국전기전자재료학회논문지
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• 제13권9호
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.465-466
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• 2006

A single-wall carbon nanotube (SWCNT) has been studied as a material of Nano-Eletro-Mechanical-System (NEMS) device together with various nanowires. In order for oscillation of a multi-wall carbon nanotube (MWCNT) or a single-walled carbon nanotube (SWCNT) on plane surface, it needs suspension of a CNT across trench electrodes. So we propose fabrication method of a MWCNT resonator using dielectrophoresis and show successful results of suspeneded MWNT. Thin electrodes with large gaps could not suspend small diameter MWNT but thicker electrodes could. Thin MWNT could be suspended only when the electrode gap was reduced.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.486-489
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• 2007

Carbon nanotube (CNT) cathodes having a trench structure similar to the structure of the gated triodetype cathode were successfully fabricated by a screenprinting method with multi-walled carbon nanotubes. We observed that a liquid method not only readily removes the organic residues on the CNT films, but also satisfactorily protrudes the CNTs out of the electrode surface. The CNT cathodes prepared by the liquid method showed a turned-on field of $1.4\;V/{\mu}m$. The emission current density of them was about $3.1\;mA/cm^2$ at the electric field of $3\; V/{\mu}m$. The liquid method appears to be a promising surface treatment of CNT cathode for gated triode-type FEDs applications.

• ETRI Journal
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• 제35권4호
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• pp.603-609
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• 2013

In this paper, we present a 600-V reverse conducting insulated gate bipolar transistor (RC-IGBT) for soft and hard switching applications, such as general purpose inverters. The newly developed RC-IGBT uses the deep reactive-ion etching trench technology without the thin wafer process technology. Therefore, a freewheeling diode (FWD) is monolithically integrated in an IGBT chip. The proposed RC-IGBT operates as an IGBT in forward conducting mode and as an FWD in reverse conducting mode. Also, to avoid the destructive failure of the gate oxide under the surge current and abnormal conditions, a protective Zener diode is successfully integrated in the gate electrode without compromising the operation performance of the IGBT.

• 한국재료학회지
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• 제13권5호
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• pp.333-337
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• 2003

We report a new fabrication process for carbon nanotube field emitters with high performance. The key of the fabrication process is trim-and-leveling the carbon nanotubes grown in trench structures by employing a planarization process, which leads to a uniform distance from the carbon nanotube tip to the electrode. In order to enable this processing, spin-on-glass liquid is applied over the CNTs grown in trench to have them stubborn adhesion among themselves as well as to the substrate. Thus fabricated emitters reveal an extremely stable emission and aging characteristics with a large current density of 40 ㎃/$\textrm{cm}^2$ at 4.5 V/$\mu\textrm{m}$. The field enhancement factor calculated from the F-N plot is $1.83${\times}$10^{5}$ $cm^{－1}$ , which is a very high value and indicates a superior quality of the emitter originating from the nature of open-tip and high stability of the carbon nanotubes obtained new process.

• 대한전자공학회논문지SD
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• 제39권5호
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• Transactions on Electrical and Electronic Materials
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• 제5권5호
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• pp.169-172
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• 2004

Deep sub-micron device required to get the superior ultra thin gate oxide characteristics. In this research, I will recommend a novel shallow trench isolation structure(STI) for thin gate oxide and a $N_2$O gate oxide 30 $\AA$ by NO ambient process. The local oxidation of silicon(LOCOS) isolation has been replaced by the shallow trench isolation which has less encroachment into the active device area. Also for $N_2$O gate oxide 30 $\AA$, ultra thin gate oxide 30 $\AA$ was formed by using the $N_2$O gate oxide formation method on STI structure and LOCOS structure. For the metal electrode and junction, TiSi$_2$ process was performed by RTP annealing at 850 $^{\circ}C$ for 29 sec. In the viewpoints of the physical characteristics of MOS capacitor, STI structure was confirmed by SEM. STI structure was expected to minimize the oxide loss at the channel edge. Also, STI structure is considered to decrease the threshold voltage, result in a lower Ti/TiN resistance( Ω /cont.) and higher capacitance-gate voltage(C- V) that made the STI structure more effective. In terms of the TDDB(sec) characteristics, the STI structure showed the stable value of 25 % ～ 90 % more than 55 sec. In brief, analysis of the ultra thin gate oxide 30 $\AA$ proved that STI isolation structure and salicidation process presented in this study. I could achieve improved electrical characteristics and reliability for deep submicron devices with 30 $\AA$ $N_2$O gate oxide.

• 한국재료학회지
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• 제14권8호
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• pp.542-546
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• 2004

We report a new fabrication process for high performance triode type CNT field emitters and their superior electrical properties. The CNT-based triode-type field emitter structure was fabricated by the conventional semiconductor processes. The keys of the fabrication process are spin-on-glass coating and trim-and-leveling of the carbon nanotubes grown in trench structures by employing a chemical mechanical polishing process. They lead to strong adhesion and a uniform distance from the carbon nanotube tips to the electrode. The measured emission property of the arrays showed a remarkably uniform and high current density. The gate leakage current could be remarkably reduced by coating of thin $SiO_{2}$ insulating layer over the gate metal. The field enhancement factor(${\beta}$) and emission area(${\alpha}$) were calculated from the F-N plot. This process can be applicable to fabrication of high power CNT vacuum transistors with good electrical performance.