• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.52-56
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• 2014

In this paper, a high-efficiency power amplifier is implemented using a gate and drain bias control circuit for WPT (Wireless Power Transmission). This control circuit has been employed to improve the PAE (Power Added Efficiency). The gate and drain bias control circuits consists of a directional coupler, power detector, and operation amplifier. A high gain two-stage amplifier using a drive amplifier is used for the low input stage of the power amplifier. The proposed power amplifier that uses a gate and drain bias control circuit can have high efficiency at a low and high power level. The PAE has been improved up to 80.5%.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1033-1034
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• 2005

High resolution 2.1” QVGA LTPS LCD (190ppi) having high aperture ratio of 65% could be successfully developed using state-of-the-art SLS technology and active/gate storage structure. Cost effective P-MOS 6-Mask structure was used. Full gate and transmission gate circuits are integrated in the panel. The high aperture ratio was obtained by using active/gate capacitance structure, which can reduce storage capacitance area. The aperture ratio was increased to 65% from 49% of conventional gate/data capacitance structure. The brightness was increased from 180cd to 270cd without any degradation of optical properties such as contrast ratio, flicker or crosstalk.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.31 no.2 s.257
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• pp.151-158
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• 2007

The mechanism of power transmission from motor torque to stem thrust and the operation characteristic of each stroke position are analyzed using the diagnostic signal, and effects of differential pressure on the performance of motor operated flexible wedge gate valve are investigated. Test facility consists of 76 mm motor operated valve(flexible wedge type), pump and pipe system. Static and dynamic test are performed separately, and two differential pressure conditions are applied in the dynamic test. To evaluate the performance of valve, test signals for the torque, thrust, current, voltage and stroke length are acquired by using UDS which is diagnosis device for motor operated valve, and each diagnostic signal is analyzed and compared. The characteristic of valve performance factors such as stem factor, rate of loading, valve factor, are evaluated, and these factors are found to be severely influenced by the fluid differential pressure.

• Journal of the Korean institute of surface engineering
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• v.33 no.4
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• pp.217-221
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• 2000

The gate oxide thickness is becoming thinner and thinner in order to speed up the semiconductor CMOS devices. We have investigated very thin$ SiO_2$ gate oxide layers and found anomaly between the thickness determined with capacitance measurement and these obtained with cross-sectional high resolution transmission electron microscopy. The thicknesses difference of the two becomes important for the thickness of the oxide below 5nm. We propose that the variation of dielectric constant in thin oxide films cause the anomaly. We modeled the behavior as (equation omitted) and determined $\varepsilon_{bulk}$=3.9 and $\varepsilon_{int}$=-4.0. We predict that optimum $SiO_2$ gate oxide thickness may be $20\AA$ due to negative contribution of the interface dielectric constant. These new results have very important implication for designing the CMOS devices.s.

• Proceedings of the KIPE Conference
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• 1996.06a
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• pp.89-92
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• 1996

This paper describes a detailed simulation model of the static condenser (STATCON) to analyze the dynamic interaction with the ac transmission line. The static condenser was represented by a 12-pulse voltage-source inverter sharing an energy storage dc capacitor. The voltage-source inverter consists of two 6-pulse bridges modeled with ideal gate-turn-off switches. The control system for the static condenser was designed through a mathematical model deduced from the equivalent circuit. Simulation results show that the conceived model is very effective to analyze the dynamic interaction between the static condenser and the ac transmission system.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.33-38
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• 2004

A multi-valued logic(MVL) pass gate is an important element to configure multi-valued logic. In this paper, we designed the Quaternary MIN(QMIN)/negated MIN(QNMIN) gate, the Quaternary MAX(QMAX)/negated MAX(QNMAX) gate using double pass-transistor logic(DPL) with neuron $MOS({\nu}MOS)$ threshold gate. DPL is improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates composed by ${\nu}MOS$ down literal circuit(DLC). The proposed gates get the valued to realize various multi threshold voltages. In this paper, these circuits are used 3V power supply voltage and parameter of 0.35um N-Well 2-poly 4-metal CMOS technology, and also represented HSPICE simulation results.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.12
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• pp.10-18
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• 1997

The parallel trabutary signals in the SDH-based transmission system have the frame phase skew due to uneven transmission delays in the data and the clock path. This phase skew must be eliminated prior to synchronously multiplexing process. A new twenty-four channel, 51.84Mb/s DFPA(Digital Frame Phase Aligner) has been designed and fabricated in 0.8.mu.m CMOS gate array. This unique device phase-aligns the skewed input signals with refernce frame synchronous signal and reference clok for subsequent synchronous multiplexing process. the performance of fabricated device is evaluated by the STM-16 transmission system and DS-3 meansurement set. The frame phase margin of +2/-3 bit periods has been demonstrated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• 전자공학회논문지 IE
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• v.44 no.2
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• pp.14-20
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• 2007

This paper presents quaternary D flip-flop with advanced performance. Quaternary D flip-flop is composed of the components such as thermometer code output circuit, EX-OR gate, bias inverter, transmission gate and binary D flip-flop circuit. The designed circuit is simulated by HSPICE in $0.35{\mu}m$ one-poly six-metal CMOS process parameters with a single +3.3V supply voltage. In the simulations, sampling frequencies is measured around 100MHz. The PDP parameters and FOM we estimated to be 59.3fJ, 33.7 respectively.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.4
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• pp.522-533
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• 2012

This paper presents an adaptive strategy of GENCOs for reducing the greenhouse gas by fuel mix change. Fuel mix stands for generation capacity portfolio composed of different fuel resources. Currently, the generation sector of power industry in Korea is heavily dependent on fossil fuels, therefore it is required to change the fuel mix gradually into more eco-friendly way based on renewable energies. The generation costs of renewable energies are still expensive compared to fossil fueled resources. This is why the adaptive change is more preferred at current stage and this paper proposes an optimal strategy for capacity planning based on multiple environmental scenarios on the time horizon. This study used the computer program tool named GATE-PRO (Generation And Transmission Expansion PROgram), which is a mixed-integer non-linear program developed by Hongik university and Korea Energy Economics Institute. The simulations have been carried out with the priority allocation method in the program to determine the optimal mix of NRE(New Renewable Energy). Through this process, the result proposes an economic fuel mix under emission constraints compatible with the greenhouse gas mitigation policy of the United Nations.