• Journal of Power Electronics
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• 제8권3호
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• pp.201-209
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• 2008

This paper presents the modeling and design of a digital controller for a phase-shifted full-bridge converter (PSFBC) in a discrete-time domain. The discretized PSFBC model is first derived and then analyzed considering the sampling effect and the system parameters. Based on this model, the digital controller is directly designed in a discrete-time domain. The simulation and experimental results are provided to show the validity of the proposed modeling and controller design.

• Journal of information and communication convergence engineering
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• 제8권4호
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• pp.461-465
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• 2010

This paper describes the design method of Time-to-Digital Converter(TDC) to obtain the constant delay time and good reliability. The reliability property is described with delay elements. In TDC the time signal is converted to digital value which is based on delay elements for the time interpolation. To obtain the constant delay time, the first and the last delay elements have different structure compared to the middle delay elements. In the first and the last delay elements, the driving ability could be controlled for the different delay time. The delay element can be designed by analog and digital devices. The delay time of the element using analog devices is not sensitive to process parameters than that of the element using digital devices. And the TDC circuit by the elements using analog devices shows better reliability than that by the elements using digital devices also.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.233-236
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• 2000

A new time-to-digital converter is designed and the converter is based on a voltage-to-frequency converter and a counter. The converter output is obtained without delay time and the resolution improves with increasing input time interval because the output of voltage-to-frequency converter increases linearly. In the designed circuit the input time intervals range is from 100nsec to 3${\mu}$ sec.

• 전기전자학회논문지
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• 제8권2호
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• pp.166-171
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• 2004

본 논문은 두 신호의 시간 차이를 디지털 신호로 변환하는 시간디지털변환기(Time to Digital Converter) 변환기에 대해서 서술하였다. 시간 차이를 측정하는 방법에는 여러 가지가 있으나 변환시간이나 저해상도의 단점을 가지고 있으며 또한 복잡한 구조를 가지는 문제점이 있다. 그러나 본 논문에서 제안한 시간디지털변환기회로는 고속 디지털 샘플러를 사용함으로써 단순한 구조로 높은 해상도(25ps)를 실현할 수 있었다. 입력신호가 시간디지털변환기의 입력으로 들어오면 샘플러가 신호를 검출해내고 레지스터에 의해 처리된 후 코딩블럭에 의해서 코딩되게 된다. 또한 25ps의 해상도를 얻기 위해서 본 논문에서는 다중위상클록발생기를 구현하였다.

• 전기전자학회논문지
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• 제27권3호
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• pp.234-238
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• 2023

본 논문에서는 PVT(process, voltage, and temperature) 변화에 대한 보상기능을 가지는 시간-디지털 변환기(time-to-digital converter : TDC)를 제안한다. 일반적인 지연 라인(delay line) 기반의 TDC는 인버터의 전파 지연을 기반으로 시간을 측정하기 때문에 근본적으로 PVT 변화에 민감하다. 이 논문은 PVT 변화에 의한 전파 지연을 보상하여 TDC의 해상도 변화를 최소화시키는 방법을 제안한다. 또한 넓은 입력 측정 범위(detection range)를 갖기 위해 Cyclic Vernier TDC (CVTDC) 구조를 채택한다. 제안하는 PVT보상 기능의 CVTDC는 45nm CMOS 공정으로 설계되어, 8mW의 전력을 소모하며, 5 ps의 TDC 해상도 및 약 5.1 ns 입력 측정 범위를 갖는다.

• Journal of Power Electronics
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• 제11권2호
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• pp.113-119
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• 2011

This paper presents a DSP based direct digital control design and implementation for a high power boost converter. A single loop and dual loop voltage control are digitally implemented and compared. The real time workshop (RTW) is used for automatic real-time code generation. Experimental results of a 20 kW boost converter based on the TMS320F2808 DSP during reference voltage changes, input voltage changes, and load disturbances are presented. The results show that the dual loop control achieves better steady state and transient performance than the single loop control. In addition, the experimental results validate the effectiveness of using the RTW for automatic code generation to speed up the system implementation.

• 전기전자학회논문지
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• 제19권4호
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• pp.479-485
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• 2015

A resistance deviation-to-time interval converter based on dual-slope integration using second generation current conveyors (CCIIs) is designed for connecting resistive bridge sensors with a digital system. It consists of a differential integrator using CCIIs, a voltage comparator, and a digital control logic for controlling four analog switches. Experimental results exhibit that a conversion sensitivity amounts to $15.56{\mu}s/{\Omega}$ over the resistance deviation range of $0-200{\Omega}$ and its linearity error is less than ${\pm}0.02%$. Its temperature stability is less than $220ppm/^{\circ}C$ in the temperature range of $-25-85^{\circ}C$. Power dissipation of the converter is 60.2 mW.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1987년도 한국자동제어학술회의논문집; 한국과학기술대학, 충남; 16-17 Oct. 1987
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• pp.497-500
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• 1987

A new concept in resolver-to-digital conversion is described, which is based on the digital phase locked loop(DPLL). This converter receives phase modulation and converts it into digital form using time ratio techniques. In this paper, the theories on DPLL and resolver and the design of the converter are covered.

• Journal of Power Electronics
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• 제9권3호
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• pp.430-437
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• 2009

This paper presents the dynamic characteristics of buck and buck-boost dc-dc converters with digital filters. At first, the PID, the minimum phase FIR filter and the IIR filter controls are discussed in the buck dc-dc converter. Comparisons of the dynamic characteristics between the buck and buck-boost converters are then discussed. As a result, it is clarified that the superior dynamic characteristics are realized in the IIR filter method. In the buck converter, the undershoot is less than 2% and the transient time is less than 0.4ms. On the other hand, in the buck-boost converter, the undershoot is about 3%. However, the transient time is approximately over 4ms because the output capacitance is too large to suppress the output voltage ripple in this type of converter.

• Journal of information and communication convergence engineering
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• 제5권2호
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• pp.112-115
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• 2007

A CMOS TDC(time-to-digital converter) is proposed which has a simple cyclic structure. The proposed TDC consists of pulse-shrinking elements, D latches and D flip-flops. The operation is based on pulse-shrinking of the input pulse. The resolution of digital output can be easily improved by increasing the number of the pulse-shrinking elements, D latches and D flip flops. The TDC performance is improved in viewpoints of power consumption and chip area. Simulation results are shown to illustrate the performance of the proposed TDC circuit.